Integrated circuit, method for driving the same, and semiconductor device

• US 8,891,286 B2
• Filed: 04/21/2014
• Issued: 11/18/2014
• Est. Priority Date: 12/03/2010
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Endo, Masami, Ohmaru, Takuro
• Primary Examiner(s): PHAN, TRONG Q
• Application Number:
  US14/257,050
• Publication Number:
  US 20140226394A1
• Time in Patent Office: 211 Days
• Field of Search: 365/149, 365/154, 365/185.08, 365/233.1
• US Class Current: 365/149
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03K 21/403 Arrangements for storing the counting state in case of power supply interruption
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00

Abstract

An integrated circuit which can be switched to a resting state and can be returned from the resting state rapidly is provided. An integrated circuit whose power consumption can be reduced without the decrease in operation speed is provided. A method for driving the integrated circuit is provided. The integrated circuit includes a first flip-flop and a second flip-flop including a nonvolatile memory circuit. In an operating state in which power is supplied, the first flip-flop retains data. In a resting state in which supply of power is stopped, the second flip-flop retains data. On transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop. On return from the resting state to the operating state, the data is transferred from the second flip-flop to the first flip-flop.

Claims

1. A semiconductor device comprising:

a substrate including a semiconductor material;

a first flip-flop on the substrate,

wherein the first flip-flop comprises a first transistor, and

wherein a first channel formation region of the first transistor is formed in the substrate; and

a second flip-flop over the first flip-flop,

wherein the second flip-flop comprises a memory circuit,

wherein the memory circuit comprises a second transistor, and

wherein a second channel formation region of the second transistor comprises an oxide semiconductor,

wherein in an operating state in which power is supplied to the first flip-flop and the second flip-flop, the first flip-flop retains data,

wherein in a resting state in which supply of power to the first flip-flop and the second flip-flop is stopped, the second flip-flop retains data,

wherein on transition from the operating state into the resting state, the data is transferred from the first flip-flop to the second flip-flop, and

wherein on transition from the resting state into the operating state, the data is transferred from the second flip-flop to the first flip-flop.

2. The semiconductor device according to claim 1 further comprising a selection circuit to which output data from the second flip-flop is input and which selectively outputs any one piece of the data input,

wherein output data from the selection circuit is input to the first flip-flop, and output data from the first flip-flop is input to the second flip-flop.

3. The semiconductor device according to claim 1,

wherein the second flip-flop further comprises an arithmetic portion,

wherein the memory circuit further comprises a storage capacitor,

wherein in the memory circuit:

output data from the first flip-flop is input to a first electrode of the second transistor;

a second electrode of the second transistor is electrically connected to a first electrode of the storage capacitor;

a second electrode of the storage capacitor is grounded; and

the first electrode of the storage capacitor and the second electrode of the second transistor forms a node,

wherein the arithmetic portion includes a logic circuit,

wherein the logic circuit includes a third transistor whose gate electrode is electrically connected to the node, and

wherein the arithmetic portion performs operation in accordance with data retained in the node.

4. The semiconductor device, according to claim 1, wherein the substrate is a single crystal semiconductor substrate of silicon.

5. The semiconductor device, according to claim 1, wherein the substrate is an SOI substrate.

6. The semiconductor device, according to claim 1, wherein the oxide semiconductor comprises In, Ga and Zn.

7. A semiconductor device comprising:

a substrate including a semiconductor material;

a first flip-flop on the substrate,

wherein the first flip-flop comprises a first transistor, and

wherein a first channel formation region of the first transistor is formed in the substrate; and

a second flip-flop over the first flip-flop,

wherein the second flip-flop comprises a memory circuit,

wherein the memory circuit comprises a second transistor, and

wherein a second channel formation region of the second transistor comprises an oxide semiconductor,

wherein before a resting state in which supply of power to the first flip-flop and the second flip-flop is stopped, data retained in the first flip-flop is transferred to the second flip-flop,

wherein in the resting state, the data is retained in the second flip-flop, and

wherein after the resting state, the data in the first flip-flop is restored by the second flip-flop.

8. The semiconductor device according to claim 7 further comprising a selection circuit to which output data from the second flip-flop is input and which selectively outputs any one piece of the data input,

wherein output data from the selection circuit is input to the first flip-flop, and output data from the first flip-flop is input to the second flip-flop.

9. The semiconductor device according to claim 7,

wherein the second flip-flop further comprises an arithmetic portion,

wherein the memory circuit further comprises a storage capacitor,

wherein in the memory circuit:

output data from the first flip-flop is input to a first electrode of the first transistor;

a second electrode of the second transistor is electrically connected to a first electrode of the storage capacitor;

a second electrode of the storage capacitor is grounded; and

the first electrode of the storage capacitor and the second electrode of the second transistor forms a node,

wherein the arithmetic portion includes a logic circuit,

wherein the logic circuit includes a third transistor whose gate electrode is electrically connected to the node, and

wherein the arithmetic portion performs operation in accordance with data retained in the node.

10. The semiconductor device, according to claim 7, wherein the substrate is a single crystal semiconductor substrate of silicon.

11. The semiconductor device, according to claim 7, wherein the substrate is an SOI substrate.

12. The semiconductor device, according to claim 7, wherein the oxide semiconductor comprises In, Ga and Zn.

13. A semiconductor device comprising:

a substrate including a semiconductor material;

a first flip-flop on the substrate,

wherein the first flip-flop comprises a first transistor, and

wherein a channel formation region of the first transistor is formed in the substrate; and

a second flip-flop over the first flip-flop,

wherein the second flip-flop comprises a second transistor including an oxide semiconductor in a semiconductor layer,

wherein the second flip-flop includes;

a memory circuit that includes the second transistor and a storage capacitor; and

an arithmetic portion,

wherein one electrode of the second transistor is electrically connected to a first electrode of the storage capacitor,

wherein the arithmetic portion includes a third transistor, and

wherein a gate electrode of the third transistor is electrically connected to the one electrode of the second transistor.

14. The semiconductor device according to claim 13 further comprising a selection circuit which is electrically connected to the first flip-flop and the second flip-flop.

15. The semiconductor device, according to claim 13, wherein the substrate is a single crystal semiconductor substrate of silicon.

16. The semiconductor device, according to claim 13, wherein the substrate is an SOI substrate.

17. The semiconductor device, according to claim 13, wherein the oxide semiconductor comprises In, Ga and Zn.