Semiconductor memory device capable of measuring write current and method for measuring write current

• US 8,891,323 B2
• Filed: 12/19/2012
• Issued: 11/18/2014
• Est. Priority Date: 08/29/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ahn, Chang Yong, Em, Ho Seok
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US13/720,974
• Publication Number:
  US 20140063905A1
• Time in Patent Office: 699 Days
• Field of Search: 365/145, 365/148, 365/158, 365/163, 365/189.07, 365/189.16, 365/201, 365/220, 365/189.04
• US Class Current: 365/201
• CPC Class Codes: G11C 11/21 using electric elements
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/00 Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
• CPC Class Codes: G11C 16/00 Erasable programmable read-only memories G11C14/00 takes precedence
• CPC Class Codes: G11C 2029/5006 Current
• CPC Class Codes: G11C 29/50 Marginal testing, e.g. race, voltage or current testing
• CPC Class Codes: G11C 29/50008 of impedance

Abstract

A method for measuring a write current of a semiconductor memory device includes the steps of: programming initial data into memory cells which are to be programmed substantially at the same time; determining whether the memory cells are programmed into the same state or not; inputting test data when the memory cells are programmed into the same state; setting write current paths of the memory cells by comparing the initial data and the test data; and measuring a write current consumed when the test data are programmed into the memory cells.

Claims

1. A method for measuring a write current of a semiconductor memory device, comprising the steps of:

selecting a memory cell whose write current is to be measured among memory cells,

programming initial data into the memory cells which are to be programmed at substantially the same time;

determining whether the memory cells are programmed into a same state or not;

inputting test data when the memory cells are programmed into the same state, wherein a selected bit of the test data is configured to have an opposite logical level to a corresponding bit of the initial data and the selected bit is to be programmed into the selected memory cell;

setting write current paths of the memory cells by comparing the initial data and the test data; and

measuring the write current of the selected memory cell when the test data are programmed into the memory cells.

2. The method according to claim 1, wherein the step of setting the write current paths comprises the step of forming a write current path of the selected memory cell.

3. The method according to claim 1, wherein the initial data programmed into the respective memory cells are at a logic low level,

the selected bit of the test data programmed into the selected memory cell is at a logic high level, and

other bits of the test data programmed into other memory cells except the selected memory cell of the memory cells are at a logic low level.

4. The method according to claim 1, wherein the initial data programmed into the respective memory cells are at a logic high level,

the selected bit of the test data programmed into the selected memory cell is at a logic low level, and

other bits of the test data programmed into other memory cells except the selected memory cell of the memory cells are at a logic high level.

5. A semiconductor memory device comprising:

a plurality of memory cells configured to be programmed at substantially the same time, wherein the memory cells comprise a selected memory cell whose write current is to be measured;

a plurality of write drivers allocated to the respective memory cells and configured to provide a write current set according to the state of input data to the respective memory cells; and

a plurality of write current path control units allocated to the respective memory cells and configured to compare initial data programmed into the respective memory cells to test data to be programmed into the respective memory cells and set a write current path between the memory cells and the corresponding write drivers according to the comparison result, during a test operation,

wherein bits of the initial data are configured to have the same logical levels, wherein a selected bit of the test data is configured to have an opposite logical level to a corresponding bit of the initial data and the selected bit is to be programmed into the selected memory cell.

6. The semiconductor memory device according to claim 5, wherein when the initial data and the test data have opposite values, the write current path control units form write current paths between the corresponding memory cells and the corresponding write drivers.

7. The semiconductor memory device according to claim 6, wherein the write current path control units are formed inside the corresponding write drivers, respectively.

8. The semiconductor memory device according to claim 7, wherein the write drivers comprise current sources for applying a write current to the respective memory cells, and

the write current path control units enable the current sources of the corresponding write drivers.

9. The semiconductor memory device according to claim 7, further comprising bit lines connected between the write drivers and the memory cells, respectively.

10. The semiconductor memory device according to claim 6, wherein the write current path control units are formed outside the corresponding write drivers.

11. The semiconductor memory device according to claim 10, further comprising switches connected between the memory cells and the write drivers, and

the write current path control units form the write current paths according to control of the corresponding switches.

12. The semiconductor memory device according to claim 11, further comprising bit lines connected between the switches and the write drivers.

13. The semiconductor memory device according to claim 5, wherein each of the write current path control units comprises:

an initial data storing block configured to store the initial data; and

a compare block configured to compare the initial data stored in the initial data storing block to the test data, and output a control signal for setting the write current path according to the comparison result.

14. The semiconductor memory device according to claim 5, wherein the memory cells are connected to different input/output pins.

15. The semiconductor memory device according to claim 5, wherein the memory cells comprise a memory element and a selecting element, the memory element having a variable resistance value depending on an applied current to the memory element.