Reducing write amplification in a flash memory
First Claim
1. An apparatus comprising:
- a memory circuit comprising (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses; and
a manager configured to (i) receive a plurality of data items and respective host addresses in a random order from one or more applications, (ii) transform said respective host addresses to said memory addresses, (iii) write said data items in an active one of a plurality of regions in said memory circuit and (iv) mark said memory addresses in said active region that store said data items as used, wherein (a) said applications are executed in one or more computers, (b) said memory addresses in said active region are accessed in a sequential order while writing said data items to minimize a write amplification and (c) said random order is preserved between said data items while writing in said active region.
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Abstract
An apparatus having a memory circuit and a manager is disclosed. The memory circuit generally has (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses. The manager may be configured to (i) receive data items in a random order from one or more applications, (ii) write the data items in an active one of a plurality of regions in a memory circuit and (iii) mark the memory addresses in the active region that store the data items as used. Each data item generally has a respective host address. The applications may be executed in one or more computers. The memory addresses in the active region may be accessed in a sequential order while writing the data items to minimize a write amplification. The random order is generally preserved between the data items while writing in the active region.
10 Citations
20 Claims
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1. An apparatus comprising:
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a memory circuit comprising (i) one or more Flash memories and (ii) a memory space that spans a plurality of memory addresses; and a manager configured to (i) receive a plurality of data items and respective host addresses in a random order from one or more applications, (ii) transform said respective host addresses to said memory addresses, (iii) write said data items in an active one of a plurality of regions in said memory circuit and (iv) mark said memory addresses in said active region that store said data items as used, wherein (a) said applications are executed in one or more computers, (b) said memory addresses in said active region are accessed in a sequential order while writing said data items to minimize a write amplification and (c) said random order is preserved between said data items while writing in said active region. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for reducing write amplification in a Flash memory, comprising the steps of:
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(A) receiving a plurality of data items and respective host addresses in a random order at a manager from one or more applications executed in one or more computers; (B) transforming said respective host addresses to said memory addresses; (C) writing said data items in an active one of a plurality of regions in a memory circuit, wherein (i) said memory circuit comprises (a) one or more of said Flash memories and (b) a memory space that spans a plurality of memory addresses, (ii) said memory addresses in said active region are accessed in a sequential order while writing said data items to minimize said write amplification and (iii) said random order is preserved between said data items while writing in said active region; and (D) marking said memory addresses in said active region that store said data items as used. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
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Specification