Memory subsystem hibernation

• US 8,892,831 B2
• Filed: 08/18/2008
• Issued: 11/18/2014
• Est. Priority Date: 01/16/2008
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: Khmelnitsky, Vadim, Wakrat, Nir Jacob
• Primary Examiner(s): Rigol, Yaima
• Application Number:
  US12/193,551
• Publication Number:
  US 20090182962A1
• Time in Patent Office: 2,283 Days
• Field of Search: 711/103, 711/115, 365226-229
• US Class Current: 711/162
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In a managed memory subsystem, information associated with the memory subsystem is copied from volatile memory in the memory subsystem to host system memory. The copying can be over a standard interface. Responsive to memory subsystem power up from a powered down state or power loss, the information is copied from the host system memory back to the volatile memory in the memory subsystem, where the information can be used by the memory subsystem to perform memory operations. Transferring information from host system memory to volatile memory in a memory subsystem is faster and more power efficient than transferring the same information from non-volatile memory to volatile memory in the memory subsystem.

Claims

1. A method comprising:

copying state information from a volatile memory of a managed memory system into a non-volatile memory included in the managed memory system, wherein the state information includes information used to map logical sector requests from a host system to the non-volatile memory;

copying address information from the volatile memory of the managed memory system to a volatile memory of the host system coupled to the managed memory system, wherein the address information includes a physical address of the state information stored in the non-volatile memory;

responsive to a power-related trigger event, reading the address information from the volatile host system memory; and

using the physical address included in the address information read from the volatile memory of the host system to access the state information stored in the non-volatile memory.

2. The method of claim 1, wherein the managed memory system is a managed NAND memory system.

3. The method of claim 1, wherein the address information is copied over a bus that conforms to at least one of the following standard bus protocols:

Advanced Technology Attachment (ATA), MultiMediaCard (MMC) and Secure Digital (SD).

4. The method of claim 1, wherein the volatile memory of the managed memory system is accessible by an embedded controller in the managed memory system.

5. The method of claim 1, further comprising detecting the power-related trigger event by the managed memory system.

6. The method of claim 1, wherein the power-related trigger event comprises the managed memory system powering up from a powered down or power loss state.

7. A memory system, comprising:

a host system comprising volatile memory; and

a managed memory system comprising volatile memory and non-volatile memory, wherein information related to the managed memory system is stored in the volatile memory, and wherein the managed memory system comprises a processor configured to;

copy state information from the volatile memory of the managed memory system into the non-volatile memory of the managed memory system, wherein the state information includes information used to map logical sector requests from the host system to the non-volatile memory of the managed memory system;

copy address information from the volatile memory of the managed memory system to the volatile memory of the host system, wherein the address information includes a physical address of the state information stored in the non-volatile memory;

read, responsive to a power-related trigger event, the address information from the volatile host system memory; and

use the physical address included in the address information read from the volatile memory of the host system to access the state information stored in the non-volatile memory.

8. The memory system of claim 7, wherein the managed memory system is a managed NAND memory system.

9. The memory system of claim 7, wherein the address information is copied over a bus that conforms to at least one of the following bus protocols:

Advanced Technology Attachment (ATA), MultiMediaCard (MMC) and Secure Digital (SD).

10. The memory system of claim 7, wherein the processor is further configured to detect the power-related trigger event.

11. The memory system of claim 7, wherein the power-related trigger event comprises the managed memory system powering up from a powered down or power loss state.