Optimization of source, mask and projection optics

0Associated
Cases 
0Associated
Defendants 
0Accused
Products 
15Forward
Citations 
0
Petitions 
1
Assignment
First Claim
1. A method implemented by a computer for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method comprising:
 defining a model of the lithographic process using a plurality of design variables including projection opticsrelated design variables;
defining a multivariable cost function representing a lithographic process response, wherein the multivariable cost function comprises a function of the projection opticsrelated design variables; and
reconfiguring, using the computer, characteristics of the lithographic process by adjusting the projection opticsrelated design variables, until a predefined termination condition for the multivariable cost function is satisfied.
1 Assignment
0 Petitions
Accused Products
Abstract
Embodiments of the present invention provide methods for optimizing a lithographic projection apparatus including optimizing projection optics therein, and preferably including optimizing a source, a mask, and the projection optics. The projection optics is sometimes broadly referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape wavefront in the lithographic projection apparatus, enabling aberration control of the overall imaging process. According to the embodiments herein, the optimization can be accelerated by iteratively using linear fitting algorithm or using Taylor series expansion using partial derivatives of transmission cross coefficients (TCCs).
64 Citations
View as Search Results
DETERMINATION METHOD, STORAGE MEDIUM AND INFORMATION PROCESSING APPARATUS  
Patent #
US 20130010272A1
Filed 06/27/2012

Current Assignee
Canon Kabushiki Kaisha

Sponsoring Entity
Canon Kabushiki Kaisha

DESIGN RULE AND LITHOGRAPHIC PROCESS COOPTIMIZATION  
Patent #
US 20150089459A1
Filed 04/16/2013

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

METHODS AND SYSTEMS FOR PATTERN DESIGN WITH TAILORED RESPONSE TO WAVEFRONT ABERRATION  
Patent #
US 20150153651A1
Filed 12/18/2014

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Rule and lithographic process cooptimization  
Patent #
US 9,489,479 B2
Filed 04/16/2013

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Determination method, storage medium and information processing apparatus  
Patent #
US 9,551,926 B2
Filed 06/27/2012

Current Assignee
Canon Kabushiki Kaisha

Sponsoring Entity
Canon Kabushiki Kaisha

Level faults interception in integrated circuits  
Patent #
US 9,697,310 B2
Filed 11/02/2015

Current Assignee
Winbond Electronics Corporation Of America

Sponsoring Entity
Winbond Electronics Corporation Of America

Flows of optimization for lithographic processes  
Patent #
US 10,025,201 B2
Filed 02/13/2015

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Discrete source mask optimization  
Patent #
US 10,191,384 B2
Filed 02/04/2014

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Image log slope (ILS) optimization  
Patent #
US 10,394,131 B2
Filed 02/09/2016

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Optimization flows of source, mask and projection optics  
Patent #
US 10,401,732 B2
Filed 03/06/2017

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Methods and systems for pattern design with tailored response to wavefront aberration  
Patent #
US 10,423,075 B2
Filed 12/18/2014

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Flows of optimization for lithographic processes  
Patent #
US 10,459,346 B2
Filed 07/16/2018

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Discrete source mask optimization  
Patent #
US 10,558,124 B2
Filed 01/25/2019

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Method and apparatus to correct for patterning process error  
Patent #
US 10,691,863 B2
Filed 09/26/2016

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Method and apparatus to correct for patterning process error  
Patent #
US 10,719,011 B2
Filed 09/27/2016

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Constrained Optimization Of Lithographic Source Intensities Under Contingent Requirements  
Patent #
US 20110096313A1
Filed 10/26/2009

Current Assignee
GlobalFoundries Inc.

Sponsoring Entity
International Business Machines Corporation

Pattern Selection for FullChip Source and Mask Optimization  
Patent #
US 20110099526A1
Filed 10/28/2010

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Photolithographic process simulation including efficient result computation for multiple process variation values  
Patent #
US 7,921,383 B1
Filed 02/12/2007

Current Assignee
oLambda Inc

Sponsoring Entity
Olambda Inc

System and method for creating a focusexposure model of a lithography process  
Patent #
US 7,747,978 B2
Filed 08/02/2006

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

METHODS AND SYSTEM FOR MODELBASED GENERIC MATCHING AND TUNING  
Patent #
US 20100146475A1
Filed 11/05/2009

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Method for process window optimized optical proximity correction  
Patent #
US 7,694,267 B1
Filed 02/02/2007

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Method and system for topographyaware reticle enhancement  
Patent #
US 7,814,456 B2
Filed 11/04/2005

Current Assignee
Tela Innovations Inc.

Sponsoring Entity
Tela Innovations Inc.

METHOD AND SYSTEM FOR LITHOGRAPHY PROCESSWINDOWMAXIMIXING OPTICAL PROXIMITY CORRECTION  
Patent #
US 20100162197A1
Filed 12/18/2009

Current Assignee
ASML Netherlands BV

Sponsoring Entity
Brion Technologies Incorporated

PATTERN SELECTION FOR LITHOGRAPHIC MODEL CALIBRATION  
Patent #
US 20100122225A1
Filed 11/05/2009

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

SCANNER MODEL REPRESENTATION WITH TRANSMISSION CROSS COEFFICIENTS  
Patent #
US 20100141925A1
Filed 10/29/2009

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Methods and system for lithography process window simulation  
Patent #
US 20090157360A1
Filed 12/05/2008

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Layout printability optimization method and system  
Patent #
US 7,568,179 B1
Filed 09/21/2006

Current Assignee
Armen Kroyan, Julia Kroyan

Sponsoring Entity
Armen Kroyan, Julia Kroyan

Optical metrology model optimization based on goals  
Patent #
US 7,588,949 B2
Filed 01/29/2007

Current Assignee
Tokyo Electron Limited

Sponsoring Entity
Tokyo Electron Limited

System and method for mask verification using an individual mask error model  
Patent #
US 7,587,704 B2
Filed 09/08/2006

Current Assignee
ASML Netherlands BV

Sponsoring Entity
Brion Technologies Incorporated

Source optimization for image fidelity and throughput  
Patent #
US 7,623,220 B2
Filed 06/28/2007

Current Assignee
Mentor Graphics Corporation

Sponsoring Entity
Mentor Graphics Corporation

SYSTEM AND METHOD FOR MODIFYING A DATA SET OF A PHOTOMASK  
Patent #
US 20090307649A1
Filed 06/10/2008

Current Assignee
Cadence Design Systems Incorporated

Sponsoring Entity
Cadence Design Systems Incorporated

LENS HEATING COMPENSATION SYSTEMS AND METHODS  
Patent #
US 20090296055A1
Filed 05/29/2009

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Model and parameter selection for optical metrology  
Patent #
US 7,330,279 B2
Filed 07/25/2002

Current Assignee
Tokyo Electron America Incorporated

Sponsoring Entity
Timbre Technologies Incorporated

Method of manufacturing reliability checking and verification for lithography process using a calibrated eigen decomposition model  
Patent #
US 7,342,646 B2
Filed 01/27/2005

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Masktools B.V.

Source optimization for image fidelity and throughput  
Patent #
US 20080174756A1
Filed 06/28/2007

Current Assignee
Mentor Graphics Corporation

Sponsoring Entity
Mentor Graphics Corporation

SYSTEM AND METHOD FOR CREATING A FOCUSEXPOSURE MODEL OF A LITHOGRAPHY PROCESS  
Patent #
US 20070031745A1
Filed 08/02/2006

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Lithographic apparatus and method for optimizing illumination using a photolithographic simulation  
Patent #
US 7,245,356 B2
Filed 11/17/2005

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Layout generation and optimization to improve photolithographic performance  
Patent #
US 7,266,803 B2
Filed 07/29/2005

Current Assignee
Taiwan Semiconductor Manufacturing Company Limited

Sponsoring Entity
Taiwan Semiconductor Manufacturing Company Limited

System and method for lithography simulation  
Patent #
US 7,003,758 B2
Filed 04/01/2004

Current Assignee
ASML Netherlands BV

Sponsoring Entity
Brion Technologies Incorporated

Method and apparatus for providing lens aberration compensation by illumination source optimization  
Patent #
US 7,034,919 B2
Filed 11/12/2003

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Masktools B.V.

Printing a mask with maximum possible process window through adjustment of the source distribution  
Patent #
US 7,057,709 B2
Filed 12/04/2003

Current Assignee
GlobalFoundries Inc.

Sponsoring Entity
International Business Machines Corporation

Method for computing partially coherent aerial imagery  
Patent #
US 20050015233A1
Filed 07/17/2003

Current Assignee
International Business Machines Corporation

Sponsoring Entity
International Business Machines Corporation

Photogrammetry engine for model construction  
Patent #
US 6,912,293 B1
Filed 06/25/1999

Current Assignee
Carl P. Korobkin

Sponsoring Entity
Carl P. Korobkin

Adaptive real time control of a reticle/mask system  
Patent #
US 20050167514A1
Filed 01/30/2004

Current Assignee
Tokyo Electron Limited

Sponsoring Entity
Tokyo Electron Limited

Method and apparatus for providing lens aberration compensation by illumination source optimization  
Patent #
US 20040184030A1
Filed 11/12/2003

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Masktools B.V.

Source and mask optimization  
Patent #
US 20040265707A1
Filed 03/31/2004

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Optical proximity correction  
Patent #
US 6,541,167 B2
Filed 04/24/2001

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Masktools Netherlands B.V.

Method for designing a refractive or reflective optical system and method for designing a diffraction optical element  
Patent #
US 6,567,226 B2
Filed 03/01/1999

Current Assignee
Sumitomo Electric Industries Limited

Sponsoring Entity
Sumitomo Electric Industries Limited

Optical proximity correction method utilizing serifs having variable dimensions  
Patent #
US 6,670,081 B2
Filed 06/11/2001

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Masktools Netherlands B.V.

Differential interferometer system and lithographic stepandscan apparatus provided with such a system  
Patent #
US 6,046,792 A
Filed 03/06/1997

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASM Lithography Incorporated

Twodimensionally balanced positioning device with two object holders, and lithographic device provided with such a positioning device  
Patent #
US 5,969,441 A
Filed 10/10/1997

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASM Lithography Incorporated

Optical proximity correction method for intermediatepitch features using subresolution scattering bars on a mask  
Patent #
US 5,821,014 A
Filed 02/28/1997

Current Assignee
ASML Netherlands BV

Sponsoring Entity
Microunity Systems Engineering Incorporated

Method for generating proximity correction features for a lithographic mask pattern  
Patent #
US 5,663,893 A
Filed 05/03/1995

Current Assignee
ASML Netherlands BV

Sponsoring Entity
Microunity Systems Engineering Incorporated

Method and system for optimizing illumination in an optical photolithography projection imaging system  
Patent #
US 5,680,588 A
Filed 06/06/1995

Current Assignee
Canon Kabushiki Kaisha

Sponsoring Entity
International Business Machines Corporation

Method and apparatus for patterning and imaging member  
Patent #
US 5,523,193 A
Filed 12/21/1994

Current Assignee
Texas Instruments Inc.

Sponsoring Entity
Texas Instruments Inc.

Illumination device  
Patent #
US 5,296,891 A
Filed 10/29/1992

Current Assignee
FraunhoferGesellschaft zur Forderung der angewandten Forschung e.V.

Sponsoring Entity
FraunhoferGesellschaft zur Forderung der angewandten Forschung e.V.

Exposure device including an electrically aligned electronic mask for micropatterning  
Patent #
US 5,229,872 A
Filed 01/21/1992

Current Assignee
Goodrich Corporation

Sponsoring Entity
Hughes Aircraft Company

METHOD FOR OPTIMIZING SOURCE AND MASK TO CONTROL LINE WIDTH ROUGHNESS AND IMAGE LOG SLOPE  
Patent #
US 20120052418A1
Filed 08/31/2010

Current Assignee
GlobalFoundries Inc.

Sponsoring Entity
International Business Machines Corporation

Optimization Flows of Source, Mask and Projection Optics  
Patent #
US 20120113404A1
Filed 11/09/2011

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

PatternDependent Proximity Matching/Tuning Including Light Manipulation By Projection Optics  
Patent #
US 20120117521A1
Filed 11/09/2011

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

Determining calibration parameters for a lithographic process  
Patent #
US 8,285,030 B2
Filed 03/15/2010

Current Assignee
Synopsys Incorporated

Sponsoring Entity
Synopsys Incorporated

Method for optimizing source and mask to control line width roughness and image log slope  
Patent #
US 8,372,565 B2
Filed 08/31/2010

Current Assignee
GlobalFoundries Inc.

Sponsoring Entity
International Business Machines Corporation

LENS HEATING AWARE SOURCE MASK OPTIMIZATION FOR ADVANCED LITHOGRAPHY  
Patent #
US 20130212543A1
Filed 01/29/2013

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

METHOD AND APPARATUS FOR ENHANCING SIGNAL STRENGTH FOR IMPROVED GENERATION AND PLACEMENT OF MODELBASED SUBRESOLUTION ASSIST FEATURES (MBSRAF)  
Patent #
US 20130311960A1
Filed 05/13/2013

Current Assignee
ASML Netherlands BV

Sponsoring Entity
ASML Netherlands BV

20 Claims
 1. A method implemented by a computer for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method comprising:
defining a model of the lithographic process using a plurality of design variables including projection opticsrelated design variables; defining a multivariable cost function representing a lithographic process response, wherein the multivariable cost function comprises a function of the projection opticsrelated design variables; and reconfiguring, using the computer, characteristics of the lithographic process by adjusting the projection opticsrelated design variables, until a predefined termination condition for the multivariable cost function is satisfied.  View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20)
1 Specification
This application claims priority to U.S. Provisional Application No. 61/412,372, filed Nov. 10, 2010, the contents of which are incorporated by reference herein in its entirety.
The claimed invention relates to lithographic apparatuses and processes, and more particularly to tools for simultaneously or alternatively optimizing illumination sources, masks/design layouts and projection optics for use in lithographic apparatuses and processes.
A lithographic projection apparatus can be used, for example, in the manufacture of integrated circuits (ICs). In such a case, a mask may contain a circuit pattern corresponding to an individual layer of the IC (“design layout”), and this circuit pattern can be transferred onto a target portion (e.g. comprising one or more dies) on a substrate (e.g., silicon wafer) that has been coated with a layer of radiationsensitive material (“resist”), by methods such as irradiating the target portion through the circuit pattern on the mask. In general, a single substrate contains a plurality of adjacent target portions to which the circuit pattern is transferred successively by the lithographic projection apparatus, one target portion at a time. In one type of lithographic projection apparatuses, the circuit pattern on the entire mask is transferred onto one target portion in one go; such an apparatus is commonly referred to as a wafer stepper. In an alternative apparatus, commonly referred to as a stepandscan apparatus, a projection beam scans over the mask in a given reference direction (the “scanning” direction) while synchronously moving the substrate parallel or antiparallel to this reference direction. Different portions of the circuit pattern on the mask are transferred to one target portion progressively. Since, in general, the lithographic projection apparatus will have a magnification factor M (generally <1), the speed F at which the substrate is moved will be a factor M times that at which the projection beam scans the mask. More information with regard to lithographic devices as described herein can be gleaned, for example, from U.S. Pat. No. 6,046,792, incorporated herein by reference.
Prior to transferring the circuit pattern from the mask to the substrate, the substrate may undergo various procedures, such as priming, resist coating and a soft bake. After exposure, the substrate may be subjected to other procedures, such as a postexposure bake (PEB), development, a hard bake and measurement/inspection of the transferred circuit pattern. This array of procedures is used as a basis to make an individual layer of a device, e.g., an IC. The substrate may then undergo various processes such as etching, ionimplantation (doping), metallization, oxidation, chemomechanical polishing, etc., all intended to finish off the individual layer of the device. If several layers are required in the device, then the whole procedure, or a variant thereof, will have to be repeated for each layer. Eventually, a device will be present in each target portion on the substrate. These devices are then separated from one another by a technique such as dicing or sawing, whence the individual devices can be mounted on a carrier, connected to pins, etc.
As noted, microlithography is a central step in the manufacturing of ICs, where patterns formed on substrates define functional elements of the ICs, such as microprocessors, memory chips etc. Similar lithographic techniques are also used in the formation of flat panel displays, microelectro mechanical systems (MEMS) and other devices.
As semiconductor manufacturing processes continue to advance, the dimensions of functional elements have continually been reduced while the amount of functional elements, such as transistors, per device has been steadily increasing over decades, following a trend commonly referred to as “Moore'"'"'s law”. At the current state of technology, layers of devices are manufactured using lithographic projection apparatuses that project a design layout onto a substrate using illumination from a deepultraviolet illumination source, creating individual functional elements having dimensions well below 100 nm, i.e. less than half the wavelength of the light from the illumination source.
This process in which features with dimensions smaller than the classical resolution limit of a lithographic projection apparatus are printed, is commonly known as lowk_{1 }lithography, according to the resolution formula CD=k_{1}×λ/NA, where λ is the wavelength of radiation employed (currently in most cases 248 nm or 193 nm), NA is the numerical aperture of projection optics in the lithographic projection apparatus, CD is the “critical dimension”—generally the smallest feature size printed—and k_{1 }is an empirical resolution factor. In general, the smaller k_{1 }the more difficult it becomes to reproduce a pattern on the wafer that resembles the shape and dimensions planned by a circuit designer in order to achieve particular electrical functionality and performance. To overcome these difficulties, sophisticated finetuning steps are applied to the lithographic projection apparatus as well as to the design layout. These include, for example, but not limited to, optimization of NA and optical coherence settings, customized illumination schemes, use of phase shifting masks, optical proximity correction (OPC, sometimes also referred to as “optical and process correction”) in the design layout, or other methods generally defined as “resolution enhancement techniques” (RET).
As one important example, OPC addresses the fact that the final size and placement of an image of the design layout projected on the substrate will not be identical to, or simply depend only on the size and placement of the design layout on the mask. It is noted that the terms “mask” and “reticle” are utilized interchangeably herein. Also, person skilled in the art will recognize that, especially in the context of lithography simulation/optimization, the term “mask” and “design layout” can be used interchangeably, as in lithography simulation/optimization, a physical mask is not necessarily used but a design layout can be used to represent a physical mask. For the small feature sizes and high feature densities present on some design layout, the position of a particular edge of a given feature will be influenced to a certain extent by the presence or absence of other adjacent features. These proximity effects arise from minute amounts of light coupled from one feature to another and/or nongeometrical optical effects such as diffraction and interference. Similarly, proximity effects may arise from diffusion and other chemical effects during postexposure bake (PEB), resist development, and etching that generally follow lithography.
In order to ensure that the projected image of the design layout is in accordance with requirements of a given target circuit design, proximity effects need to be predicted and compensated for, using sophisticated numerical models, corrections or predistortions of the design layout. The article “FullChip Lithography Simulation and Design Analysis—How OPC Is Changing IC Design”, C. Spence, Proc. SPIE, Vol. 5751, pp 114 (2005) provides an overview of current “modelbased” optical proximity correction processes. In a typical highend design almost every feature of the design layout requires some modification in order to achieve high fidelity of the projected image to the target design. These modifications may include shifting or biasing of edge positions or line widths as well as application of “assist” features that are intended to assist projection of other features.
Application of modelbased OPC to a target design requires good process models and considerable computational resources, given the many millions of features typically present in a chip design. However, applying OPC is generally not an “exact science”, but an empirical, iterative process that does not always compensate for all possible proximity effect. Therefore, effect of OPC, e.g., design layouts after application of OPC and any other RET, need to be verified by design inspection, i.e. intensive fullchip simulation using calibrated numerical process models, in order to minimize the possibility of design flaws being built into the manufacturing of a mask. This is driven by the enormous cost of making highend masks, which run in the multimillion dollar range, as well as by the impact on turnaround time by reworking or repairing actual masks once they have been manufactured.
Both OPC and fullchip RET verification may be based on numerical modeling systems and methods as described, for example in, U.S. Pat. No. 7,003,758 and an article titled “Optimized Hardware and Software For Fast, Full Chip Simulation”, by Y. Cao et al., Proc. SPIE, Vol. 5754, 405 (2005).
In addition to optimization to design layouts or masks (e.g., OPC), the illumination source can also optimized, either jointly with mask optimization or separately, in an effort to improve the overall lithography fidelity. Since the 1990s, many offaxis illumination sources, such as annular, quadrupole, and dipole, have been introduced, and have provided more freedom for OPC design, thereby improving the imaging results, As is known, offaxis illumination is a proven way to resolve fine structures (i.e., target features) contained in the mask. However, when compared to a traditional illumination source, an offaxis illumination source usually provides less light intensity for the aerial image (AI). Thus, it becomes necessary to attempt to optimize the illumination source to achieve the optimal balance between finer resolution and reduced light intensity. The terms “illumination source” and “source” are used interchangeably in this document.
Numerous illumination source optimization approaches can be found, for example, in an article by Rosenbluth et al., titled “Optimum Mask and Source Patterns to Print A Given Shape”, Journal of Microlithography, Microfabrication, Microsystems 1(1), pp. 1320, (2002). The source is partitioned into several regions, each of which corresponds to a certain region of the pupil spectrum. Then, the source distribution is assumed to be uniform in each source region and the brightness of each region is optimized for process window. However, such an assumption that the source distribution is uniform in each source region is not always valid, and as a result the effectiveness of this approach suffers. In another example set forth in an article by Granik, titled “Source Optimization for Image Fidelity and Throughput”, Journal of Microlithography, Microfabrication, Microsystems 3(4), pp. 509522, (2004), several existing source optimization approaches are overviewed and a method based on illuminator pixels is proposed that converts the source optimization problem into a series of nonnegative least square optimizations. Though these methods have demonstrated some successes, they typically require multiple complicated iterations to converge. In addition, it may be difficult to determine the appropriate/optimal values for some extra parameters, such as y in Granik'"'"'s method, which dictates the tradeoff between optimizing the source for wafer image fidelity and the smoothness requirement of the source.
For low k_{1 }photolithography, optimization of both the source and mask is very useful to ensure a viable process window for projection of critical circuit patterns. Some algorithms (e.g. Socha et. al. Proc. SPIE vol. 5853, 2005, p. 180) discretize illumination into independent source points and mask into diffraction orders in the spatial frequency domain, and separately formulate a cost function (which is defined as a function of selected design variables) based on process window metrics such as exposure latitude which could be predicted by optical imaging models from source point intensities and mask diffraction orders. The term “design variables” as used herein means a set of parameters of a lithographic projection apparatus, for example, parameters a user of the lithographic projection apparatus can adjust. It should be appreciated that any characteristics of a lithographic projection apparatus, including those of the source, the mask, the projection optics, can be among the design variables in the optimization. The cost function is often a nonlinear function of the design variables. Then standard optimization techniques are used to minimize the cost function.
One problem with these algorithms that formulate a cost function is that they require a large number of full forward optical imaging model simulations before convergence on both optimal source and mask is reached. Optimizing the lithographic projection apparatus using a clip (which is defined as a portion of a design layout with calibration features that can be used for optimization of the lithographic projection apparatus, as elaborated further in the detailed description section) of medium complexity can take weeks or even months on latest standard PC hardware, which is generally considered impractical. A practical optimization process generally costs less than about 24 hours.
Relatedly, the delay of EUV lithography and the pressure of ever decreasing design rules have driven semiconductor chipmakers to move deeper into the low k_{1 }lithography era with existing 193 nm ArF lithography. Lithography towards lower k_{1 }puts heavy demands on RET, exposure tools, and the need for lithofriendly design. The 1.35 ArF hyper numerical apertures (NA) exposure tool will be the exposure tool for chip manufactures to use in the next two years. To ensure that circuit design can be produced on to the substrate with workable process window; sourcemask optimization (SMO) is becoming an important RET that is required for 2× nm node.
A source and mask (design layout) optimization method and system that allow for simultaneous optimization of the source and mask using a cost function without constraints and within a practicable amount of time is described in a commonly assigned International Patent Application No. PCT/US2009/065359, filed on Nov. 20, 2009, and published as WO2010/059954, titled “Fast Freeform Source and Mask CoOptimization Method”, which is hereby incorporated by reference in its entirety.
New development in hardware and software of lithographic projection apparatuses provides more flexibility by making projection optics therein adjustable. The term “projection optics” as used herein should be broadly interpreted as encompassing various types of optical systems, including refractive optics, reflective optics, apertures and catadioptric optics, for example. The term “projection optics” may also include components operating according to any of these design types for directing, shaping or controlling the projection beam of radiation, collectively or singularly. The term “projection optics” may include any optical component in the lithographic projection apparatus, no matter where the optical component is located on an optical path of the lithographic projection apparatus. Projection optics can include optical components for shaping, adjusting and/or projecting light from the source before the light passes the mask, and/or optical components for shaping, adjusting and/or projecting the light after the light passes the mask. The projection optics generally exclude the source and the mask.
For example, adjustable parameters (“knobs”) of the projection optics make it possible to shape light in more degrees of freedom (e.g., wavefront shape, intensity distribution, etc.) and/or to accommodate a wider range of conditions of the source and the mask (namely to provide a larger process window (PW)), than what is offered by the existing SMO techniques.
However, optimizing these additional knobs entails very high computation cost. Therefore, methods to simplify and accelerate optimization of these knobs related to the projection optics jointly with knobs associated with the source and mask is desirable.
Therefore what is needed is a computationallyefficient comprehensive optimization method for characterizing a lithographic process based on which the setting of a lithographic apparatus (including setting of a projection optics system) is decided and a mask is designed.
Embodiments as described herein provide methods for improving or optimizing a lithographic projection apparatus including improving or optimizing projection optics therein, and preferably including the capability of improving or optimizing a source, a mask, and the projection optics, simultaneously or alternatively. The projection optics is sometimes referred to as “lens”, and therefore the joint optimization process may be termed source mask lens optimization (SMLO). Another term used to describe the SMLO process is source mask pupil optimization (SMPO), as in certain embodiments, lens optimization is done for the pupil plane of the projection optics. However, the scope of the invention is not restricted to optimization in the pupil plane only. SMLO is desirable over existing source mask optimization process (SMO), partially because including the projection optics in the optimization can lead to a larger process window by introducing a plurality of adjustable characteristics of the projection optics. The projection optics can be used to shape a wavefront in the lithographic projection apparatus. According to the embodiments herein, the optimization can be accelerated. Although adjustable characteristics of the projection optics, the source and the mask are used in the description of the embodiments, other adjustable characteristics of the lithographic projection apparatus, such as, dose and focus, can be adjusted in the optimization.
The embodiments herein improve or optimize the lithographic projection apparatus by minimizing a suitable cost function of design variables that can be characteristics of the source, projection optics, and the mask. Nonlimiting examples of the cost function are given. Other forms of the cost function are also possible and can accommodate a wide variety of lithography metrics. The cost function can be a linear or nonlinear function of the design variables.
Methods of simultaneous SMLO and alternative SMLO have been disclosed. The SMLO process can be accelerated by combining the SMLO with a various pattern selection methods.
The above aspects and other aspects and features of the present invention will become apparent to those ordinarily skilled in the art upon review of the following description of specific embodiments of the invention in conjunction with the accompanying figures, wherein:
Although specific reference may be made in this text to the use of the invention in the manufacture of ICs, it should be explicitly understood that the invention has many other possible applications. For example, it may be employed in the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, liquidcrystal display panels, thinfilm magnetic heads, etc. The skilled artisan will appreciate that, in the context of such alternative applications, any use of the terms “reticle”, “wafer” or “die” in this text should be considered as interchangeable with the more general terms “mask”, “substrate” and “target portion”, respectively.
In the present document, the terms “radiation” and “beam” are used to encompass all types of electromagnetic radiation, including ultraviolet radiation (e.g. with a wavelength of 365, 248, 193, 157 or 126 nm) and EUV (extreme ultraviolet radiation, e.g. having a wavelength in the range 520 nm).
The term “optimizing” and “optimization” as used herein mean adjusting a lithographic projection apparatus such that results and/or processes of lithography have more desirable characteristics, such as higher accuracy of projection of design layouts on a substrate, larger process windows, etc.
Further, the lithographic projection apparatus may be of a type having two or more substrate tables (and/or two or more mask tables). In such “multiple stage” devices the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposures. Twin stage lithographic projection apparatuses are described, for example, in U.S. Pat. No. 5,969,441, incorporated herein by reference.
The mask referred to above comprise design layouts. The design layouts can be generated utilizing CAD (computeraided design) programs, this process often being referred to as EDA (electronic design automation). Most CAD programs follow a set of predetermined design rules in order to create functional design layouts/masks. These rules are set by processing and design limitations. For example, design rules define the space tolerance between circuit devices (such as gates, capacitors, etc.) or interconnect lines, so as to ensure that the circuit devices or lines do not interact with one another in an undesirable way. The design rule limitations are typically referred to as “critical dimensions” (CD). A critical dimension of a circuit can be defined as the smallest width of a line or hole or the smallest space between two lines or two holes. Thus, the CD determines the overall size and density of the designed circuit. Of course, one of the goals in integrated circuit fabrication is to faithfully reproduce the original circuit design on the substrate (via the mask).
The term mask as employed in this text may be broadly interpreted as referring to generic patterning means that can be used to endow an incoming radiation beam with a patterned crosssection, corresponding to a pattern that is to be created in a target portion of the substrate; the term “light valve” can also be used in this context. Besides the classic mask (transmissive or reflective; binary, phaseshifting, hybrid, etc.), examples of other such patterning means include:
 a programmable mirror array. An example of such a device is a matrixaddressable surface having a viscoelastic control layer and a reflective surface. The basic principle behind such an apparatus is that (for example) addressed areas of the reflective surface reflect incident light as diffracted light, whereas unaddressed areas reflect incident light as undiffracted light. Using an appropriate filter, the said undiffracted light can be filtered out of the reflected beam, leaving only the diffracted light behind; in this manner, the beam becomes patterned according to the addressing pattern of the matrixaddressable surface. The required matrix addressing can be performed using suitable electronic means. More information on such mirror arrays can be gleaned, for example, from U.S. Pat. Nos. 5,296,891 and 5,523,193, which are incorporated herein by reference.
 a programmable LCD array. An example of such a construction is given in U.S. Pat. No. 5,229,872, which is incorporated herein by reference.
As a brief introduction,
In an optimization process of a system, a figure of merit of the system can be represented as a cost function. The optimization process boils down to a process of finding a set of parameters (design variables) of the system that minimizes the cost function. The cost function can have any suitable form depending on the goal of the optimization. For example, the cost function can be weighted root mean square (RMS) of deviations of certain characteristics (evaluation points) of the system with respect to the intended values (e.g., ideal values) of these characteristics; the cost function can also be the maximum of these deviations. The term “evaluation points” herein should be interpreted broadly to include any characteristics of the system. The design variables of the system can be confined to finite ranges and/or be interdependent due to practicalities of implementations of the system. In case of a lithographic projection apparatus, the constraints are often associated with physical properties and characteristics of the hardware such as tunable ranges, and/or mask manufacturability design rules, and the evaluation points can include physical points on a resist image on a substrate, as well as nonphysical characteristics such as dose and focus.
In a lithographic projection apparatus, a source provides illumination (i.e. light); projection optics direct and shapes the illumination through a mask and onto a substrate. The term “projection optics” is broadly defined here to include any optical component that may alter the wavefront of the radiation beam. For example, projection optics may include at least some of the components 14, 16a, 16b and 16c. An aerial image (AI) is the light intensity distribution on the substrate. A resist layer on the substrate is exposed and the aerial image is transferred to the resist layer as a latent “resist image” (RI) therein. The resist image (RI) can be defined as a spatial distribution of solubility of the resist in the resist layer. A resist model can be used to calculate the resist image from the aerial image, an example of which can be found in commonly assigned U.S. Patent Application Publ. No. 2009/0157360, disclosure of which is hereby incorporated by reference in its entirety. The resist model is related only to properties of the resist layer (e.g., effects of chemical processes which occur during exposure, PEB and development). Optical properties of the lithographic projection apparatus (e.g., properties of the source, the mask and the projection optics) dictate the aerial image. Since the mask used in the lithographic projection apparatus can be changed, it is desirable to separate the optical properties of the mask from the optical properties of the rest of the lithographic projection apparatus including at least the source and the projection optics.
An exemplary flow chart for simulating lithography in a lithographic projection apparatus is illustrated in
More specifically, it is noted that the source model 31 can represent the optical characteristics of the source that include, but not limited to, NAsigma (cy) settings as well as any particular illumination source shape (e.g. offaxis light sources such as annular, quadrupole, and dipole, etc.). The projection optics model 32 can represent the optical characteristics of the of the projection optics that include aberration, distortion, refractive indexes, physical sizes, physical dimensions, etc. The design layout model 35 can also represent physical properties of a physical mask, as described, for example, in U.S. Pat. No. 7,587,704, which is incorporated by reference in its entirety. The objective of the simulation is to accurately predict, for example, edge placements and CDs, which can then be compared against an intended design. The intended design is generally defined as a preOPC design layout which can be provided in a standardized digital file format such as GDSII or OASIS or other file format.
From this design layout, one or more portions may be identified, which are referred to as “clips”. In a specific embodiment of the invention, a set of clips is extracted, which represents the complicated patterns in the design layout (typically about 50 to 1000 clips, although any number of clips may be used). As will be appreciated by those skilled in the art, these patterns or clips represent small portions (i.e. circuits, cells or patterns) of the design and especially the clips represent small portions for which particular attention and/or verification is needed. In other words, clips may be the portions of the design layout or may be similar or have a similar behavior of portions of the design layout where critical features are identified either by experience (including clips provided by a customer), by trial and error, or by running a fullchip simulation. Clips usually contain one or more test patterns or gauge patterns.
An initial larger set of clips may be provided a priori by a customer based on known critical feature areas in a design layout which require particular image optimization. Alternatively, in another embodiment of the present invention, the initial larger set of clips may be extracted from the entire design layout by using some kind of automated (such as, machine vision) or manual algorithm that identifies the critical feature areas.
To reduce the overall computation burden, various ways of optimization can be envisioned. In one embodiment, first a set of clips is selected by a pattern selection method based on diffraction signature analysis or any other method, and then the SMLO process is performed. Alternatively, first a full chip simulation is performed, ‘hot spots’ and/or ‘warm spots’ are identified from the full chip simulation, and then a pattern selection step is performed. The optimization is done based on the selected patterns. The pattern selection algorithm (based on diffraction signature analysis or other methods) can be seamlessly integrated with the SMLO process. These example methods are described further with respect to
In a lithographic projection apparatus, as an example, a cost function is expressed as
wherein (z_{1}, z_{2}, . . . , z_{N}) are N design variables or values thereof; f_{p}(z_{1}, z_{2}, . . . , z_{N}) is a difference between an actual value and an intended value of a characteristic at the pth evaluation point for a set of values of the design variables of (z_{1}, z_{2}, . . . , z_{N}). w_{p }is a weight constant assigned to the pth evaluation point. An evaluation point or pattern more critical than others can be assigned a higher w_{p }value. Patterns and/or evaluation points with larger number of occurrences may be assigned a higher w_{p }value, too. Examples of the evaluation points can be any physical point or pattern on the wafer, or any point on a virtual design layout, or resist image, or aerial image. The cost function may represent any suitable characteristics of the lithographic projection apparatus or the substrate, for instance, focus, CD, image shift, image distortion, image rotation, etc. Since it is the resist image that often dictates the circuit pattern on a substrate, the cost function often includes functions that represent some characteristics of the resist image. For example, f_{p}(z_{1}, z_{2}, . . . , z_{N}) of such an evaluation point can be simply a distance between a point in the resist image to an intended position of that point (i.e., edge placement error EPE_{p}(z_{1}, z_{2}, . . . , z_{N})). The design variables can be any adjustable parameters such as adjustable parameters of the source, the mask, the projection optics, dose, focus, etc. Preferably, at least some of the design variables are adjustable characteristics of the projection optics. The projection optics may include components collectively called as “wavefront manipulator” that can be used to adjust shapes of a wavefront and intensity distribution and/or phase shift of the irradiation beam. The projection optics preferably can adjust a wavefront and intensity distribution at any location along an optical path of the lithographic projection apparatus, such as before the mask, near a pupil plane, near an image plane, near a focal plane. The projection optics can be used to correct or compensate for certain distortions of the wavefront and intensity distribution caused by, for example, the source, the mask, temperature variation in the lithographic projection apparatus, thermal expansion of components of the lithographic projection apparatus. Adjusting the wavefront and intensity distribution can change values of the evaluation points and the cost function. Such changes can be simulated from a model or actually measured.
It should be noted that the normal weighted root mean square (RMS) of f_{p}(z_{1}, z_{2}, . . . , z_{N}) is defined as
therefore, minimizing the weighted RMS of f_{p}(z_{1}, z_{2}, . . . , z_{N}) is equivalent to minimizing the cost function
defined in Eq. 1. Thus the weighted RMS of f_{p}(z_{1}, z_{2}, . . . , z_{N}) and Eq. 1 may be utilized interchangeably for notational simplicity herein.
Further, if we are considering maximizing the PW (Process Window), we can consider the same physical location from different PW conditions as different evaluation points in the cost function in (Eq. 1). For example, if we are considering N PW conditions, then we can categorize the evaluation points according to their PW conditions and write the cost functions as:
Where f_{p}_{u}(z_{1}, z_{2}, . . . , z_{N}) is the difference between an actual value and an intended value of the p_{i}th evaluation point for a set of values of the design variables of (z_{1}, z_{2}, . . . , z_{N}) under the uth PW condition u=1, . . . , U. When this difference is the EPE, then minimizing the above cost function is equivalent to minimizing the edge shift under various PW conditions, thus this leads to maximizing the PW. In particular, if the PW also consists of different mask bias, then minimizing the above cost function also includes the minimization of MEEF (Mask Error Enhancement Factor), which is defined as the ratio between the wafer EPE and the induced mask edge bias.
The design variables may have constraints, which can be expressed as (z_{1}, z_{2}, . . . , z_{N})εZ, where Z is a set of possible values of the design variables.
The optimization process therefore is to find a set of values of the design variables, under the constraints (z_{1}, z_{2}, . . . , z_{N})εZ, that minimize the cost function, i.e., to find
A general method of optimizing the lithography projection apparatus, according to an embodiment, is illustrated in
In a lithographic projection apparatus, the source, mask and projection optics can be optimized alternatively (referred to as Alternative Optimization) or optimized simultaneously (referred to as Simultaneous Optimization), according to embodiments. The terms “simultaneous”, “simultaneously”, “joint” and “jointly” as used herein mean that the design variables of the characteristics of the source, mask, projection optics and/or any other design variables, are allowed to change at the same time. The term “alternative” and “alternatively” as used herein mean that not all of the design variables are allowed to change at the same time.
In
Persons skilled in the art will also appreciate that pattern selection algorithm, as discussed before, may be integrated with the simultaneous or alternative SMLO. For example, when an alternative SMLO is adopted, first a fullchip SMO can be performed, the ‘hot spots’and/or ‘warm spots’ are identified, then an LO or SLO (sourcelens optimization) is performed. Persons skilled in the art will appreciate in view of the present disclosure that numerous permutations and combinations of suboptimizations are possible in order to achieve the desired optimization results.
In one example embodiment shown in the flowchart in
Alternatively, we can identify the gauges through hot spots or warm spots, i.e., the defects or patterns which are almost defects. Such an alternative flow is shown in
One example SMLO method according to embodiments of the invention will be explained in connection with the flowchart in
In
As generally shown in 4304, a small subset of clips 4306 (e.g. 15 to 50 clips) is selected from the full set 4302. As will be explained in more detail below, the selection of clips is preferably performed such that the process window of the selected patterns as closely as possible matches the process window for the full set of critical patterns. The effectiveness of the selection is also measured by the total turn run time (pattern selection and SMLO) reduction.
In 4308, SMLO is performed with the selected patterns (15 to 50 patterns) 4306. More particularly, an illumination source is optimized for the selected patterns 4306. This optimization can be performed using any of a wide variety of known methods, for example those described in U.S. Patent Pub. No. 2004/0265707, the contents of which are incorporated herein by reference.
In 4310, manufacturability verification of the selected patterns 4306 is performed with the source and projection optics obtained in 4308. More particularly, verification includes performing an aerial image simulation of the selected patterns 4306 and the optimized source and projection optics and verifying that the patterns will print across a sufficiently wide process window. This verification can be performed using any of a wide variety of known methods, for example those described in U.S. Pat. No. 7,342,646, the contents of which are incorporated herein by reference.
If the verification in 4310 is satisfactory, as determined in 4312, then processing advances to full chip optimization in 4314. Otherwise, processing returns to 4308, where SMLO is performed again but with a different source or set of patterns. For example, the process performance as estimated by the verification tool can be compared against thresholds for certain process window parameters such as exposure latitude and depth of focus. These thresholds can be predetermined or set by a user.
In 4316, after the selected patterns meet lithography performance specifications as determined in 4312, the optimized source and projection optics 4314 will be used for optimization of the full set of clips.
In 4318, modelbased subresolution assist feature placement (MBSRAF) and optical proximity correction (OPC) for all the patterns in the full set of clips 4316 is performed. This process can be performed using any of a wide variety of known methods, for example those described in U.S. Pat. Nos. 5,663,893, 5,821,014, 6,541,167 and 6,670,081.
In 4320, using processes similar to step 4310, full pattern simulation based manufacturability verification is performed with the optimized source and projection optics 4314 and the full set of clips 4316 as corrected in 4318.
In 4322, the performance (e.g. process window parameters such as exposure latitude and depth of focus) of the full set of clips 4316 is compared against the subset of clips 4306. In one example embodiment, the pattern selection is considered complete and/or the source and projection optics are fully qualified for the full chip when the similar (<10%) lithography performances are obtained for both selected patterns (15 to 20) 4306 and all critical patterns (50 to 1000) 4316.
Otherwise, in 4324, hotspots are extracted, and in 4326 these hotspots are added to the subset 4306, and the process starts over. For example, hotspots (i.e. features among the full set of clips 4316 that limit process window performance) identified during verification 4320 are used for further source tuning or to rerun SMLO. The source and projection optics are considered fully converged when the process window of the full set of clips 4316 are the same between the last run and the run before the last run of 4322.
Therefore, from the above nonlimiting examples, the reader should appreciate that SMLO is readily accommodated within the existing optimization framework in various forms. We now revert to the mathematical background of a generic SMLO process.
As discussed before, optimization of the cost function (CF) is at the center of the SMLO method. CF can be an RMS value of some lithographic metric. Of course, CF(z_{1}, z_{2}, . . . , z_{N}) is not limited to RMS of f_{p}(z_{1}, z_{2}, . . . , z_{N}). CF(z_{1}, z_{2}, . . . , z_{N}) can be in any other suitable form.
In a first exemplary optimization process, no relationship between the design variables (z_{1}, z_{2}, . . . , z_{N}) and f_{p}(z_{1}, z_{2}, . . . , z_{N}) is assumed or approximated, except that f_{p}(z_{1}, z_{2}, . . . , z_{N}) is sufficiently smooth (e.g. first order derivatives
(n=1, 2, . . . N) exist), which is generally valid in a lithographic projection apparatus. An algorithm, such as the GaussNewton algorithm, the LevenbergMarquardt algorithm, the gradient descent algorithm, simulated annealing, the genetic algorithm, can be applied to find ({tilde over (z)}_{1}, {tilde over (z)}_{2}, . . . , {tilde over (z)}_{N}).
Here, the GaussNewton algorithm is used as an example. The GaussNewton algorithm is an iterative method applicable to a general nonlinear multivariable optimization problem. In the ith iteration wherein the design variables (z_{1}, z_{2}, . . . , z_{N}) take values of (z_{1i}, z_{2i}, . . . , z_{Ni}), the GaussNewton algorithm linearizes f_{p}(z_{1}, z_{2}, . . . , z_{N}) in the vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}), and then calculates values (z_{1(i+1)}, z_{2(i+1)}, . . . , z_{N(i+1)}) in the vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}) that give a minimum of CF(z_{1}, z_{2}, . . . , z_{N}). The design variables (z_{1}, z_{2}, . . . , z_{N}) take the values of (z_{1(i+1)}, z_{2(i+1)}, . . . , z_{N(i+1)}) in the (i+1)th iteration. This iteration continues until convergence (i.e. CF(z_{1}, z_{2}, . . . , z_{N}) does not reduce any further) or a preset number of iterations is reached.
Specifically, in the ith iteration, in the vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}),
Under the approximation of Eq. 3, the cost function becomes:
which is a quadratic function of the design variables (z_{1}, z_{2}, . . . , z_{N}). Every term is constant except the design variables (z_{1}, z_{2}, . . . , z_{N}).
If the design variables (z_{1}, z_{2}, . . . , z_{N}) are not under any constraints, (z_{1(i+1)}, z_{2(i+1)}, . . . , z_{N(i+1)}) can be derived by solving by N linear equations:
If the design variables (z_{1}, z_{2}, . . . , z_{N}) are under the constraints in the form of J inequalities (e.g. tuning ranges of (z_{1}, z_{2}, . . . , z_{N}))
for j=1, 2, . . . J ; and K equalities (e.g. interdependence between the design variables)
for k=1, 2, . . . K; the optimization process becomes a classic quadratic programming problem, wherein A_{nj}, B_{j}, C_{nk}, D_{k }are constants. Additional constraints can be imposed for each iteration. For example, a “damping factor” Δ_{D }can be introduced to limit the difference between (z_{1(i+1)}, z_{2(i+1)}, . . . , z_{N(i+1)}) and (z_{1i}, z_{2i}, . . . , z_{Ni}), so that the approximation of Eq. 3 holds. Such constraints can be expressed as z_{ni}−Δ_{D}≦z_{n}≦z_{ni}+Δ_{D}. (z_{i(i+1)}, z_{2(i+1)}, . . . z_{N(i+1)}) can be derived using, for example, methods described in Numerical Optimization (2^{nd }ed.) by Jorge Nocedal and Stephen J. Wright (Berlin New York: Vandenberghe. Cambridge University Press).
Instead of minimizing the RMS of f_{p}(z_{1}, z_{2}, . . . , z_{N}), the optimization process can minimize magnitude of the largest deviation (the worst defect) among the evaluation points to their intended values. In this approach, the cost function can alternatively be expressed as
wherein CL_{p }is the maximum allowed value for the pth evaluation point. This cost function represents the worst defect among the evaluation points. Optimization using this cost function minimizes magnitude of the worst defect. An iterative greedy algorithm can be used for this optimization.
The cost function of Eq. 5 can be approximated as:
wherein q is an even positive integer such as at least 4, preferably at least 10. Eq. 6 mimics the behavior of Eq. 5, while allowing the optimization to be executed analytically and accelerated by using methods such as the deepest descent method, the conjugate gradient method, etc.
Minimizing the worst defect size can also be combined with linearizing of f_{p}(z_{1}, z_{2}, . . . , z_{N}). Specifically, f_{p}(z_{1}, z_{2}, . . . , z_{N}) is approximated as in Eq. 3. Then the constraints on worst defect size are written as inequalities E_{Lp}≦f_{p}(z_{1}, z_{2}, . . . , z_{N})≦E_{Up}, wherein E_{Lp }and E_{Up }are two constants specifying the minimum and maximum allowed deviation for the pth evaluation point. Plugging Eq. 3 in, these constraints are transformed to, for p=1, . . . P,
Since Eq. 3 is generally valid only in the vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}), in case the desired constraints E_{Lp}≦f_{p}(z_{1}, z_{2}, . . . , z_{N})≦E_{Up }cannot be achieved in such vicinity, which can be determined by any conflict among the inequalities, the constants E_{Lp }and E_{Up }can be relaxed until the constraints are achievable. This optimization process minimizes the worst defect size in the vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}). Then each step reduces the worst defect size gradually, and we execute each step iteratively until certain terminating conditions are met. This will lead to optimal reduction of the worst defect size.
Another way to minimize the worst defect is to adjust the weight w_{p }in each iteration. For example, after the ith iteration, if the rth evaluation point is the worst defect, w_{r }can be increased in the (i+1)th iteration so that the reduction of that evaluation point'"'"'s defect size is given higher priority.
In addition, we can modify the cost functions in Eq. 4 and Eq. 5 by introducing a Lagrange multiplier to achieve compromise between the optimization on RMS of the defect size and the optimization on the worst defect size, i.e.,
Where λ is a preset constant that specifies the tradeoff between the optimization on RMS of the defect size and the optimization on the worst defect size. In particular, if λ=0, then this becomes Eq. 4 and we are only minimizing the RMS of the defect size; while if λ=1, then this becomes Eq. 5 and we are only minimizing the worst defect size; if 0<λ<1, then we are taking both into consideration in the optimization. Such optimization can be solved using multiple methods. For example, we can adjust the weighting in each iteration, similar to the one described previously. Alternatively, similar to minimizing the worst defect size from inequalities, we can view the inequalities of Eq. 6′ and 6″ as constraints of the design variables during solution of the quadratic programming problem. Then, we can relax the bounds on the worst defect size incrementally or increase the weight for the worst defect size incrementally, compute the cost function value for every achievable worst defect size, and choose the design variable values that minimize the total cost function as the initial point for the next step. By doing this iteratively, we can achieve the minimization of this new cost function,
The linear approximation of Eq. 3 only holds in a small vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}). If f_{p}(z_{1}, z_{2}, . . . , z_{N}) is highly nonlinear to the design variables (z_{1}, z_{2}, . . . , z_{N}), optimization using the linear approximation of Eq. 3 may take too many iterations and/or lead to a local minimum of the cost function CF(z_{1}, z_{2}, . . . , z_{N}) instead of a global minimum. This problem can be alleviated by expanding the cost function CF(z_{1}, z_{2}, . . . , z_{N}) into higher order polynomials of some design variables, especially those to which the cost function is highly nonlinear, such as cost functions involving aberrations introduced by the projection optics.
The example process flow of
The coefficients a_{p,n }and a_{p,n}_{1}_{,n}_{2 }can be fitted from a set of known values of the design variables and be derived as partial derivatives, details of which can be found in commonly assigned U.S. patent application Ser. No. 12/315,849, disclosure of which is hereby incorporated by reference in its entirety. The nonlinear approximation in Eq. 7 generally holds in a much larger vicinity of (z_{1i}, z_{2i}, . . . , z_{Ni}) than that in which the linear approximation of Eq. 3 holds, and thus leads to faster convergence and higher possibility of finding the global minimum, albeit at a higher computational cost. It should be noted that we only use the 2order polynomial approximation as an example of in this disclosure. It is straightforward to extend the methodologies to higherorder polynomial approximations or other nonpolynomial approximations.
In a second exemplary optimization process, according to embodiments, relationship between the design variables (z_{1}, z_{2}, . . . , z_{N}) and f_{p}(z_{1}, z_{2}, . . . , z_{N}) specific to a lithographic projection apparatus is harnessed to accelerate and simplify the optimization process.
In one example, the aerial image AI can be expressed as
Computation cost of TCC_{k′,k″} using Eq. 9 can be reduced by applying a Fourier transform to both sides of the Eq. 9:
wherein Ψ_{A}_{2 }and Ψ_{P }are the Fourier transform of A(k) and L(k), respectively. In Eq. 9′, the summation over (k′,k″) becomes a simple multiplication. TCC_{k′,k″} can be viewed as an inverse Fourier transform of Eq. 9′. More details can be found in “Fast TCC Algorithm for the Model Building of High NA Lithography Simulation,” by Roderick Köhle, Optical Microlithography XVIII, Proceedings of SPIE, Vol. 5754, 918929, which is hereby incorporated by reference in its entirety.
AI(x) is the aerial image in the space domain. A(k) is the source amplitude from point k on the source pupil plane. L(k) is the projection optics amplitude and phase function for point k on the lens pupil plane. The projection optics function in the space domain represents distortions caused by the projection optics to the light passing through the projection optics (e.g., distortions in amplitude, phase or both) as a function of location. M(k) is the mask function (i.e., design layout function) in the spatial frequency domain, and can be obtained from the mask function in the space domain by a Fourier transform. The mask function in the space domain represents distortions caused by the mask to the light passing through the mask (e.g., distortions in amplitude, phase or both) as a function of location. More details can be found in, for example, in U.S. Pat. No. 7,587,704, which is incorporated by reference in its entirety. A function in the space domain can be transformed to a corresponding function in the spatial frequency domain and vice versa by Fourier transform. Here, x and k are both vectors. It is further noted that although in the given example, Eq. 8 is derived from a scalar imaging model, this formalism can also be extended to a vector imaging model, where TE and TM or other polarized light components are summed separately. TCC_{k′,k″}, also called the Transmission Cross Coefficient, as defined in Eq. 9, can be viewed as a matrix, which includes optical properties of the lithographic projection apparatus excluding the mask.
Computation of the aerial image using Eq. 8 can be simplified if only dominant eigenvalues of the TCC_{k′,k″} are used. Specifically, when the TCC_{k′,k″} is diagonalized and on the largest R eigenvalues are retained, the TCC_{k′,k″} can be approximated as:
wherein λ_{r }(r=1, . . . , R) are the R largest eigenvalues and φ_{r }is the eigenvector corresponding to the eigenvalue λ_{r}.
Plugging Eq. 9 into Eq. 8,
It is noted that Eq. 10 is exact when all terms are retained in the eigenseries expansion, i.e., when R is equal to the rank of the TCC matrix.
The TCC_{k′,k″} matrix has a fixed relationship to the design variables. Once the TCC_{k′,k″} as a function of the design variables are known, the aerial image AI (x), the resist image, the f_{p}(z_{1}, z_{2}, . . . , z_{N}) and the cost function can be computed by using Eq. 8, the resist model, the specific definition of f_{p}(z_{1}, z_{2}, . . . , z_{N}) and the specific definition of the cost function (e.g. Eqs. 1, 5 and 6). Values of the design variables that minimize the cost function can then be found by using the methods described above such as the GaussNewton method. Computing the TCC_{k′,k″} as a function of the design variables, however, can entail significant computation cost, especially on the summation over k in Eq. 9.
We next use the design variables from projection optics which only affect the projection optics function as an example to illustrate how to speed up the fitting process. In a practical lithographic projection apparatus, the TCC_{k′,k″} can be well approximated as
TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}), a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }are independent from the design variables. Therefore, once TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}), a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }are computed, TCC_{k′,k″}(z_{1}, z_{2}, . . . , z_{N}) as a function of the design variables are known. TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}) can be directly calculated from the nominal condition (z_{10}, z_{20}, . . . , z_{N0}). The coefficients a_{TCC,k′,k″,n }and a_{TCC,k′k″,n}_{1}_{n}_{2 }can be fitted from a set of know values of the design variables or be derived as partial derivatives, details of which can be found in commonly assigned U.S. Patent Application Publ. No. 2009/0157360, disclosure of which is hereby incorporated by reference in its entirety. Among all the TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}), and a_{TCC,k′,k″,n}_{1}_{,n}_{2},
are independent, since a_{TCC,k′,k″,n}_{1}_{,n}_{2}=a_{TCC,k′,k″,n}_{2}_{,n}_{1}.
Once TCC_{k′,k″}(z_{10}, z_{20}, . . . z_{N0}), a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }are computed, the computation of the aerial image AI can be further simplified from Eq. 10 using an expansion with respect to the design variables (z_{1}, z_{2}, . . . , z_{N}):
Each term on the right side of Eq. 12 is referred to as pseudoaerial images. There are total 1+N+N^{2 }pseudoaerial images, among which
are independent.
Plugging Eq. 11 into Eq. 8,
Comparing Eq. 12 and Eq. 13, it can be seen that each pseudoaerial image can be computed from TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}) or one of the coefficients a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}. Namely,
a_{l,n}=Σ_{k′}Σ_{k″}a_{TCC,k′,k″,n}M(k′)M*(k″)exp(−j(k′−k″)x); (Eq. 14)
a_{l,n}_{1}_{,n}_{2}=Σ_{k′}Σ_{k″}a_{TCC,k′,k″,n}_{1}_{,n}_{2}M(k′)M*(k″)exp(−j(k′−k″)x) (Eq. 15)
TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}), a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }can be fitted from a plurality of TCC_{l,k′,k″} of the lithographic projection apparatus respectively under L distinctive sets of values of the design variables (z_{1}, z_{2}, . . . , z_{N}). TCC_{l,k′,k″} is defined as TCC_{l,k′,k″}≡TCC_{k′,k″}_{z}_{i}_{=p}_{li}, wherein p_{li }is the value of z, in the lth set of values of the design variables, i=1, . . . , N, l=1, . . . , L. Note that TCC_{l,k′,k″} are not functions of the design variables (z_{1}, z_{2}, . . . , z_{N}). A fitting error (FER) can be defined in any suitable form. The fitting process is to find TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}), a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }that minimize the fitting error (FER). An exemplary fitting error (FER) is shown below:
The nominal condition (z_{10}, z_{20}, . . . , z_{N0}) can be empirically determined to give acceptable performance to the lithographic projection apparatus. TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}) can be directly computed from (z_{10}, z_{20}, . . . , z_{N0}) or be fitted along with a We use the TCC computed from (z_{10}, z_{20}, . . . , z_{N0}) as an example in the following description.
L is at least
if TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}) is fitted with a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }L is at least
if TCC_{k′,k″}(z_{10}, z_{20}, . . . , z_{N0}) is directly calculated from the nominal condition (z_{10}, z_{20}, . . . , z_{N0}), and only a_{TCC,k′,k″} and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }are fitted. 2 to 3 times of
may be necessary for L in order to yield desired fitting accuracy. In an exemplary lithographic projection apparatus, N is from about 64 to about 192, and L can be greater than 10000. If this fitting is done directly, at least L TCC_{l,k′,k″}(l=1 . . . L) have to be computed as
TCC_{l,k′,k″}=Σ_{k}A(k)^{2}L_{l}(k+k′)L_{l}*(k+k″) (Eq. 17),
which requires substantial computation cost and/or storage cost or is even impractical for a large L, wherein A(k) is the amplitude function of the source, and L_{l}(k) is the projection optics function under the lth set of values of the design variables.
A method of computing the coefficients for polynomial expansion of TCC_{k′,k″}(z_{1}, z_{2}, . . . , z_{N}), according to an embodiment, that significantly reduces the computation cost, is detailed below.
The method comprises the following steps. The method starts with selecting L distinctive sets of values (p_{l1}, p_{l2}, . . . , p_{lN}) of the design variables (z_{1}, z_{2 }z_{N}) wherein p_{ln }is the value of z_{n }in the lth set of values of the design variables, n=1, . . . , N, l=1, . . . , L. This step is followed by computing a projection optics function L_{l}(k) for each set of values (p_{l1}, p_{l2}, . . . , p_{lN}), n=1, . . . , N, l=1, . . . , L. Note that we consider the nominal design variable values (z_{10}, z_{20}, . . . , z_{N0}) as the 0th set of values, i.e., p_{0i}=z_{i }for all n=1, . . . , N. The next step is identifying the relationship between the projection optics function L(k) and the design variables. We use a linear phase relationship (e.g., the Zernike design variables) as a nonlimiting example hereafter. For a linear phase relationship, identifying the relationship is equivalent to identifying a plurality of functions P_{n}(k) (n=1 . . . N) that are the impulse responses of the design variables. That is, if the projection optics function is L_{0}(k) when the design variables take the nominal values (z_{10}, z_{20}, . . . , z_{N0}), then when the design variables take the values (p_{l1}, p_{l2}, . . . , p_{lN}), the projection optics function becomes:
The following step involves computing a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }as linear combinations of TCC_{l,k′,k″}(l=1 . . . L) in a form of
wherein h_{l,n }and h_{l,n}_{1}_{,n}_{2 }(l=0, . . . , L, n=1, . . . , N, n_{1}=1, . . . , N, n_{2}=1, . . . , N) are constants. These constants can be solved by minimizing the fitting error FER in Eq. 16. In particular, they are computed by solving linear equations of a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}:
As described in the commonly assigned U.S. patent application Ser. No. 12/315,849, it can be shown that a which minimize Eq. 16 can always be expressed in a form of Eq. 19 and Eq. 20. The next step is computing
The following Eq. 21 and Eq. 22 are derived by plugging Eq. 18 into Eq. 17 and then into Eq. 19 and Eq. 20, respectively,
Note that
are only functions of k, k′ and k″ and can be computed prior to the summation over k in Eq. 21 and Eq. 22. The summation of Eq. 21 or Eq. 22 over k is done only once for each a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}. In total, only at most
summations over k are need to compute each a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}. This significantly reduces the computation cost compared to computation of L TCC_{l,k′,k″}, each of which requires a summation in Eq. 9 over k, wherein L can be 2 to 3 times of
The computation cost can be further decreased by applying a Fourier transform (e.g., a fast Fourier transform algorithm) to both sides of each of Eqs. 2122, similar to Eq. 9′.
As we mentioned previously, P_{n}(k) can be the Zernike polynomials. The Zernike polynomials include even Zernike polynomials and odd Zernike polynomials. The even Zernike polynomials are defined as Z_{n}^{m}(ρ,φ)=R_{n}^{m}(ρ)cos(mφ); the odd Zernike polynomials are defined as Z_{n}^{−m}(ρ,φ)=R_{n}^{m}(ρ)sin(mφ), where m and n are nonnegative integers with n≧m, φ is the azimuthal angle, and ρ is the radial distance, 0≦ρ≦1. The radial polynomials R_{n}^{m}(ρ) are defined as
when (nm) is even, and are identically 0 when (nm) is odd. For m=0, the even definition of the Zernike polynomials is used which reduces to R_{n}^{0}(ρ).
An alternative method of computing TCC_{k′,k″}(z_{1}, z_{2}, . . . , z_{N}), according to another embodiment, that also significantly reduces the computation cost, is detailed below.
The method comprises the following steps. The first step is identifying the relationship between the projection optics function L(k) and the design variables. We again use a linear phase relationship (e.g., the Zernike design variables) as a nonlimiting example thereafter, thus Eq. 18 describes the response of the projection optics function from the design variables. The next step is computing each a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }using Eq. 23, Eq. 24 and Eq. 25 shown below:
The next step is computing
In the computation of each a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}, the summation of Eqs. 2325 over k is done only once. In total, only at most
summations over k are needed to compute each a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2}.
The computation cost can be further decreased by applying a Fourier transform (e.g., a fast Fourier transform algorithm) to both sides of each of Eqs. 2325, similar to Eq. 9′.
Eq. 23, Eq. 24 and Eq. 25 are derived by considering a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }as Taylor expansion coefficients of TCC_{k′,k″}(z_{1}, z_{2}, . . . , z_{N}) rather than the fitting coefficients disclosed in Eq. 19 and Eq. 20. By Taylor expansion, a_{TCC,k′,k″,n }and a_{TCC,k′,k″,n}_{1}_{,n}_{2 }then become the firstorder and secondorder partial derivatives, respectively. In particular, we plug Eq. 9 into partial derivatives of TCC_{k′,k″}, then plug
Optimizing a lithographic projection apparatus can expand the process window. A larger process window provides more flexibility in process design and chip design. The process window can be defined as a set of focus and dose values for which the resist image are within a certain limit of the design target of the resist image. Note that all the methods discussed here may also be extended to a generalized process window definition that can be established by different or additional base parameters in addition to exposure dose and defocus. These may include, but are not limited to, optical settings such as NA, sigma, aberrations, polarization, or optical constants of the resist layer (whose effects on the imaging process are included in the optical model, i.e. the TCCs). For example, as described earlier, if the PW also consists of different mask bias, then the optimization includes the minimization of MEEF (Mask Error Enhancement Factor), which is defined as the ratio between the wafer EPE and the induced mask edge bias. The process window defined on focus and dose values only serve as an example in this disclosure. A method of maximizing the process window, according to an embodiment, is described below.
In a first step, starting from a known condition (f_{0},ε_{0}) in the process window, wherein f_{0 }is a nominal focus and ε_{0 }is a nominal dose, minimizing one of the cost functions below in the vicinity (f_{0}±Δf,ε_{0}±Δε):
If the nominal focus f_{0 }and nominal dose ε_{0 }are allowed to shift, they can be optimized jointly with the design variables (z_{1}, z_{2}, . . . , z_{N}). In the next step, (f_{0}±Δf,ε_{0}±Δε) is accepted as part of the process window, if a set of values of (z_{1}, z_{2}, . . . , z_{N}, f,ε) can be found such that the cost function is within a preset limit.
Alternatively, if the focus and dose are not allowed to shift, the design variables (z_{1}, z_{2}, . . . , z_{N}) are optimized with the focus and dose fixed at the nominal focus f_{o }and nominal dose ε_{0}. In an alternative embodiment, (f_{0}±Δf,ε_{0}±Δε) is accepted as part of the process window, if a set of values of (z_{1}, z_{2}, . . . , z_{N}) can be found such that the cost function is within a preset limit.
The methods described earlier in this disclosure can be used to minimize the respective cost functions of Eqs. 27, 27′, or 27″. If the design variables are characteristics of the projection optics, such as the Zernike coefficients, then minimizing the cost functions of Eqs. 27, 27′, or 27″ leads to process window maximization based on projection optics optimization, i.e., Lens Optimization (LO). If the design variables are characteristics of the source and mask in addition to those of the projection optics, then minimizing the cost function of Eqs. 27, 27′, or 27″ leads to process window maximizing based on simultaneous SourceMaskLensOptimization (SMLO), as illustrated in
Alternatively, when a lithographic projection apparatus works at a fixed nominal condition (f_{0},ε_{0}) in the process window, the actual focus f and dose E can deviate from the nominal focus f_{0 }and the nominal dose ε_{0}. The distribution of the focus f and dose c can follow a distribution (e.g. Gaussian distribution) around (f_{0},ε_{0}). The design variables can be optimized to minimize the probability that the resist image (e.g., solubility of the resist in the resist layer) at any evaluation point p (RI_{p}) falls out of a permitted range [T_{1},T_{2}]. More details can be found in commonly assigned U.S. patent application Ser. No. 12/642,436, the disclosure of which is hereby incorporated by reference in its entirety.
Mathematically, the goal of this optimization is to find a set of values of the design variables (z_{1}, z_{2}, . . . , z_{N}) that minimize
wherein P(f,ε) is a probability density function of the actual focus f and dose E.
For example, if the focus f and dose E follow a Gaussian distribution, with a standard deviation of f as σ_{f}, and a standard deviation of ε as σ_{ε}, the probability density function of (f,ε) is
Here, we assume that the focus f and dose ε are independent. However, other distributions (even nonGaussian distributions), thus other probability density functions, are also possible.
In this example, minimizing Eq. 28 is equivalent to maximize
The resist image at the evaluation point p, RI_{p}, is a function of the design variables (z_{1}, z_{2}, . . . , z_{N}) and the actual focus f and dose ε. RI_{p }can be expanded around the nominal condition (f_{0},ε_{0}) as:
Since the relationship between RI and the dose ε is essentially linear and the dose ε does not typically deviate from ε_{0 }more than 10%, the quadratic term of the dose ε is omitted. Plugging Eq. 30 into Eq. 29 and approximating
as (ε−ε_{0})<<1, Eq. 29′ can be further simplified as:
The methods described earlier in this disclosure can be used to minimize Eq. 31. If the design variables are characteristics of the projection optics, such as the Zernike coefficients, then minimizing Eq. 31 leads to process window maximization based on projection optics optimization.
A method of maximizing the process window according to an embodiment, thus comprises finding values of the design variables that minimize the maximum value of the probability that the resist image (e.g., solubility of the resist in the resist layer) at any evaluation point p (RI_{p}) falls out of a permitted range.
Computer system 100 may be coupled via bus 102 to a display 112, such as a cathode ray tube (CRT) or flat panel or touch panel display for displaying information to a computer user. An input device 114, including alphanumeric and other keys, is coupled to bus 102 for communicating information and command selections to processor 104. Another type of user input device is cursor control 116, such as a mouse, a trackball, or cursor direction keys for communicating direction information and command selections to processor 104 and for controlling cursor movement on display 112. This input device typically has two degrees of freedom in two axes, a first axis (e.g., x) and a second axis (e.g., y), that allows the device to specify positions in a plane. A touch panel (screen) display may also be used as an input device.
According to one embodiment of the invention, portions of the optimization process may be performed by computer system 100 in response to processor 104 executing one or more sequences of one or more instructions contained in main memory 106. Such instructions may be read into main memory 106 from another computerreadable medium, such as storage device 110. Execution of the sequences of instructions contained in main memory 106 causes processor 104 to perform the process steps described herein. One or more processors in a multiprocessing arrangement may also be employed to execute the sequences of instructions contained in main memory 106. In alternative embodiments, hardwired circuitry may be used in place of or in combination with software instructions to implement the invention. Thus, embodiments of the invention are not limited to any specific combination of hardware circuitry and software.
The term “computerreadable medium” as used herein refers to any medium that participates in providing instructions to processor 104 for execution. Such a medium may take many forms, including but not limited to, nonvolatile media, volatile media, and transmission media. Nonvolatile media include, for example, optical or magnetic disks, such as storage device 110. Volatile media include dynamic memory, such as main memory 106. Transmission media include coaxial cables, copper wire and fiber optics, including the wires that comprise bus 102. Transmission media can also take the form of acoustic or light waves, such as those generated during radio frequency (RF) and infrared (IR) data communications. Common forms of computerreadable media include, for example, a floppy disk, a flexible disk, hard disk, magnetic tape, any other magnetic medium, a CDROM, DVD, any other optical medium, punch cards, paper tape, any other physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASHEPROM, any other memory chip or cartridge, a carrier wave as described hereinafter, or any other medium from which a computer can read.
Various forms of computer readable media may be involved in carrying one or more sequences of one or more instructions to processor 104 for execution. For example, the instructions may initially be borne on a magnetic disk of a remote computer. The remote computer can load the instructions into its dynamic memory and send the instructions over a telephone line using a modem. A modem local to computer system 100 can receive the data on the telephone line and use an infrared transmitter to convert the data to an infrared signal. An infrared detector coupled to bus 102 can receive the data carried in the infrared signal and place the data on bus 102. Bus 102 carries the data to main memory 106, from which processor 104 retrieves and executes the instructions. The instructions received by main memory 106 may optionally be stored on storage device 110 either before or after execution by processor 104.
Computer system 100 also preferably includes a communication interface 118 coupled to bus 102. Communication interface 118 provides a twoway data communication coupling to a network link 120 that is connected to a local network 122. For example, communication interface 118 may be an integrated services digital network (ISDN) card or a modem to provide a data communication connection to a corresponding type of telephone line. As another example, communication interface 118 may be a local area network (LAN) card to provide a data communication connection to a compatible LAN. Wireless links may also be implemented. In any such implementation, communication interface 118 sends and receives electrical, electromagnetic or optical signals that carry digital data streams representing various types of information.
Network link 120 typically provides data communication through one or more networks to other data devices. For example, network link 120 may provide a connection through local network 122 to a host computer 124 or to data equipment operated by an Internet Service Provider (ISP) 126. ISP 126 in turn provides data communication services through the worldwide packet data communication network, now commonly referred to as the “Internet” 128. Local network 122 and Internet 128 both use electrical, electromagnetic or optical signals that carry digital data streams. The signals through the various networks and the signals on network link 120 and through communication interface 118, which carry the digital data to and from computer system 100, are exemplary forms of carrier waves transporting the information.
Computer system 100 can send messages and receive data, including program code, through the network(s), network link 120, and communication interface 118. In the Internet example, a server 130 might transmit a requested code for an application program through Internet 128, ISP 126, local network 122 and communication interface 118. In accordance with the invention, one such downloaded application provides for the illumination optimization of the embodiment, for example. The received code may be executed by processor 104 as it is received, and/or stored in storage device 110, or other nonvolatile storage for later execution. In this manner, computer system 100 may obtain application code in the form of a carrier wave.
 a radiation system IL, for supplying a projection beam B of radiation. In this particular case, the radiation system also comprises a radiation source SO;
 a first object table (mask table) MT provided with a mask holder for holding a mask MA (e.g., a reticle), and connected to first positioning means for accurately positioning the mask with respect to item PS;
 a second object table (substrate table) WT provided with a substrate holder for holding a substrate W (e.g., a resistcoated silicon wafer), and connected to second positioning means for accurately positioning the substrate with respect to item PS;
 a projection system (“lens”) PS (e.g., a refractive, catoptric or catadioptric optical system) for imaging an irradiated portion of the mask MA onto a target portion C (e.g., comprising one or more dies) of the substrate W.
As depicted herein, the apparatus is of a transmissive type (i.e., has a transmissive mask). However, in general, it may also be of a reflective type, for example (with a reflective mask). Alternatively, the apparatus may employ another kind of patterning means as an alternative to the use of a mask; examples include a programmable mirror array or LCD matrix.
The source SO (e.g., a mercury lamp or excimer laser) produces a beam of radiation. This beam is fed into an illumination system (illuminator) IL, either directly or after having traversed conditioning means, such as a beam expander Ex, for example. The illuminator IL may comprise adjusting means AD for setting the outer and/or inner radial extent (commonly referred to as σouter and σinner, respectively) of the intensity distribution in the beam. In addition, it will generally comprise various other components, such as an integrator IN and a condenser CO. In this way, the beam B impinging on the mask MA has a desired uniformity and intensity distribution in its crosssection.
It should be noted with regard to
The beam PB subsequently intercepts the mask MA, which is held on a mask table MT. Having traversed the mask MA, the beam B passes through the lens PL, which focuses the beam B onto a target portion C of the substrate W. With the aid of the second positioning means (and interferometric measuring means IF), the substrate table WT can be moved accurately, e.g. so as to position different target portions C in the path of the beam PB. Similarly, the first positioning means can be used to accurately position the mask MA with respect to the path of the beam B, e.g., after mechanical retrieval of the mask MA from a mask library, or during a scan. In general, movement of the object tables MT, WT will be realized with the aid of a longstroke module (coarse positioning) and a shortstroke module (fine positioning), which are not explicitly depicted in
The depicted tool can be used in two different modes:
 In step mode, the mask table MT is kept essentially stationary, and an entire mask image is projected in one go (i.e., a single “flash”) onto a target portion C. The substrate table WT is then shifted in the x and/or y directions so that a different target portion C can be irradiated by the beam PB;
 In scan mode, essentially the same scenario applies, except that a given target portion C is not exposed in a single “flash”. Instead, the mask table MT is movable in a given direction (the socalled “scan direction”, e.g., the y direction) with a speed v, so that the projection beam B is caused to scan over a mask image; concurrently, the substrate table WT is simultaneously moved in the same or opposite direction at a speed V=Mv, in which M is the magnification of the lens PL (typically, M=¼ or ⅕). In this manner, a relatively large target portion C can be exposed, without having to compromise on resolution.
The concepts disclosed herein may simulate or mathematically model any generic imaging system for imaging sub wavelength features, and may be especially useful with emerging imaging technologies capable of producing wavelengths of an increasingly smaller size. Emerging technologies already in use include EUV (extreme ultra violet) lithography that is capable of producing a 193 nm wavelength with the use of an ArF laser, and even a 157 nm wavelength with the use of a Fluorine laser. Moreover, EUV lithography is capable of producing wavelengths within a range of 205 nm by using a synchrotron or by hitting a material (either solid or a plasma) with high energy electrons in order to produce photons within this range.
The invention may further be described using the following clauses:
1. A computerimplemented method for improving a lithographic process for imaging a portion of a design layout onto a substrate using a lithographic projection apparatus comprising an illumination source and projection optics, the method comprising:
defining a multivariable cost function of a plurality of design variables that are characteristics of the lithographic process, at least some of the design variables being characteristics of the projection optics; and
reconfiguring the characteristics of the lithographic process by adjusting the design variables until a predefined termination condition is satisfied.
2. The method of clause 1, wherein the improvement process includes iteratively minimizing the cost function by calculating linear fitting coefficients within predefined relatively small neighborhoods around a starting point in each iteration.
3. The method of clause 2, wherein the cost function is minimized by a method selected from a group consisting of the GaussNewton algorithm, the LevenbergMarquardt algorithm, the gradient descent algorithm, simulated annealing, and the genetic algorithm.
4. The method of clause 1, wherein the cost function is minimized by solving polynomials, including higherorder polynomials of the design variables.
5. The method of clause 4, wherein the cost function is expanded in terms of fitting constant coefficients.
6. The method of clause 5, wherein the fitting constant coefficients are computed from coefficients from polynomial expansion of transmission cross coefficients (TCCs).
7. The method of clause 6, wherein the fitting coefficients from polynomial expansion of transmission cross coefficients (TCCs) are computed from impulse response of the design variables.
8. The method of clause 6, comprising computing partial derivatives of the transmission cross coefficients.
9. The method of clause 8, wherein the partial derivatives of the transmission cross coefficients are computed from impulse response of the design variables.
While the concepts disclosed herein may be used for imaging on a substrate such as a silicon wafer, it shall be understood that the disclosed concepts may be used with any type of lithographic imaging systems, e.g., those used for imaging on substrates other than silicon wafers.
The descriptions above are intended to be illustrative, not limiting. Thus, it will be apparent to one skilled in the art that modifications may be made to the embodiments as described without departing from the scope of the claims set out below.