Area and power saving standard cell methodology

• US 8,893,063 B2
• Filed: 04/09/2013
• Issued: 11/18/2014
• Est. Priority Date: 09/13/2007
• Status: Active Grant

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Malek-Khosravi, Behnam, Brunolli, Michael
• Primary Examiner(s): Siek, Vuthe
• Assistant Examiner(s): DIMYAN, MAGID Y
• Application Number:
  US13/859,512
• Publication Number:
  US 20130214380A1
• Time in Patent Office: 588 Days
• Field of Search: 716/100, 716/102, 716/104
• US Class Current: 716/104
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: H01L 27/04 the substrate being a semiconductor body

Abstract

A semiconductor integrated circuit including a circuit for adaptive power supply regulation and designed using a process that increases operating speed used for characterizing circuit operation at a slow corner. In some embodiments a slow corner voltage is set to a higher than expected level for timing analysis performed by automated design tools.

Claims

1. A semiconductor integrated circuit, the semiconductor integrated circuit including a circuit for adaptive power supply regulation, the semiconductor integrated circuit including gates in standard cells selected by a process using an automated design tool that

determines a first voltage for a slow corner based on timing requirements indicated by a register transfer level description, and

uses a second voltage in performing timing analysis for the slow corner, the second voltage being higher than the first voltage.

2. The semiconductor integrated circuit of claim 1, wherein the process also

determines a third voltage for a fast corner based on timing requirements indicated by the register transfer level description, and

uses a fourth voltage in performing timing analysis for the fast corner, the fourth voltage being lower than the third voltage.

3. The semiconductor integrated circuit of claim 1, wherein the process also specifies requirements for the integrated circuit, the requirements including a signal path providing for a speed comparison function, the speed comparison function used for affecting an operational characteristic of power lines of the integrated circuit.

4. The semiconductor integrated circuit of claim 2, wherein the process also specifies requirements for the integrated circuit, the requirements including a signal path providing for a speed comparison function, the speed comparison function used for affecting an operational characteristic of power lines of the integrated circuit.

5. The semiconductor integrated circuit of claim 4, wherein the operational characteristic of power lines of the integrated circuit comprises a voltage.

6. The semiconductor integrated circuit of claim 5, wherein the speed comparison function affects the operational characteristic of power lines of the integrated circuit to produce the second voltage when the signal path operates at the slow corner and the fourth voltage when the signal path operates at the fast corner.

7. The semiconductor integrated circuit of claim 2, wherein the second voltage and the fourth voltage comprise substantially the same voltage.

8. The semiconductor integrated circuit of claim 2, wherein the second voltage and the fourth voltage comprise different voltages.

9. The semiconductor integrated circuit of claim 2, wherein the process also specifies requirements for the integrated circuit including dynamic voltage scaling, translates the requirements to generate the register transfer level description, synthesizes the register transfer level description, and performs place and route operations on a gate level representation provided by the synthesized register transfer level description, utilizing the fourth voltage in order to determine whether a circuit representation provided by the place and route operations meets a timing requirement for the fast corner.

10. The semiconductor integrated circuit of claim 9, wherein the process synthesizes the register transfer level description by selecting cells from a standard cell library to implement functions in accordance with the register transfer level description, the selection of cells based in part on timing requirements indicated by the register transfer level description and determines if the selected cells meet the timing requirements indicated by the register transfer level description for both the slow corner and the fast corner, the slow corner being determined at least in part by a slow process parameter, a slow voltage parameter, and a slow temperature parameter, the fast corner being determined at least in part by a fast process parameter, a fast voltage parameter, and a fast temperature parameter, with the slow voltage parameter approximate the fast voltage parameter.

11. The semiconductor integrated circuit of claim 1, wherein the circuit for adaptive power supply regulation comprises a voltage regulation circuit.

12. The semiconductor integrated circuit of claim 1, wherein the process also specifies requirements for the integrated circuit including dynamic voltage scaling, translates the requirements to generate the register transfer level description, synthesizes the register transfer level description, and performs place and route operations on a gate level representation provided by the synthesized register transfer level description, utilizing the second voltage in order to determine whether a circuit representation provided by the place and route operations meets a timing requirement for the slow corner.