System and method for lithography simulation

• US 8,893,067 B2
• Filed: 08/20/2013
• Issued: 11/18/2014
• Est. Priority Date: 10/07/2003
• Status: Expired due to Fees

• Current Assignee: ASML Netherlands BV (ASML Holding NV)
• Original Assignee: ASML Netherlands BV (ASML Holding NV)
• Inventors: Ye, Jun, Lu, Yen-Wen, Cao, Yu, Chen, Luoqi, Chen, Xun
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US13/971,381
• Publication Number:
  US 20130332894A1
• Time in Patent Office: 455 Days
• Field of Search: 716/111, 716/51, 716/54, 716/55, 703/15, 700/95, 700/110, 700/120, 700/121, 430/4, 378/34, 382/144, 382/154
• US Class Current: 716/111
• CPC Class Codes: G03F 1/00 Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
• CPC Class Codes: G03F 7/004 Photosensitive materials G03F7/12, G03F7/14 take precedence
• CPC Class Codes: G03F 7/705 Modelling or simulating from physical phenomena up to complete wafer processes or whole workflow in wafer productions
• CPC Class Codes: G03F 7/70666 Aerial image, i.e. measuring the image of the patterned exposure light at the image plane of the projection system
• CPC Class Codes: G06F 2119/18 Manufacturability analysis or optimisation for manufacturability
• CPC Class Codes: G06F 30/20 Design optimisation, verification or simulation optimisation, verification or simulation of circuit designs G06F30/30
• CPC Class Codes: G06F 30/333 Design for testability [DFT], e.g. scan chain or built-in self-test [BIST]
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection
• CPC Class Codes: G16Z 99/00 Subject matter not provided for in other main groups of this subclass
• CPC Class Codes: G21K 5/00 Irradiation devices discharge tubes for irradiating H01J37/00

Abstract

In one aspect, the present invention is directed to a technique of, and system for simulating, verifying, inspecting, characterizing, determining and/or evaluating the lithographic designs, techniques and/or systems, and/or individual functions performed thereby or components used therein. In one embodiment, the present invention is a system and method that accelerates lithography simulation, inspection, characterization and/or evaluation of the optical characteristics and/or properties, as well as the effects and/or interactions of lithographic systems and processing techniques.

Claims

1. A system for performing a simulation of a lithographic process for fabricating an integrated circuit represented by circuit design data comprising a plurality of polygons, the system comprising:

a managing computer processor that converts the plurality of polygons in the circuit design data into a pixel-based bitmap representation of the integrated circuit; and

a plurality of specially programmed computer processors, coupled to the managing computer processor, that each perform a respective portion of the simulation using the pixel-based bitmap representation of the integrated circuit,

wherein the managing computer combines the respective portions to form an overall result of the simulation.

2. A system according to claim 1, wherein the respective portions are respective areas of the pixel-based bitmap.

3. A system according to claim 2, wherein each of the plurality of specially programmed computer processors calculates a simulated aerial image corresponding to the respective area of the pixel-based bitmap.

4. A system according to claim 3, wherein the overall result of the simulation is an overall simulated aerial image of the entire integrated circuit based on a combination of the simulated aerial images calculated for all of the respective areas of the pixel-based bitmaps.

5. A system according to claim 2, wherein each of the plurality of specially programmed computer processors calculates a simulated resist image corresponding to the respective area of the pixel-based bitmap.

6. A system according to claim 2, wherein the managing computer processor determines each respective portion performed by the plurality of specially programmed processors.

7. A system according to claim 1, wherein the circuit design data includes resolution enhancement technology.

8. A system according to claim 1, further comprising a design database for storing the circuit design data, wherein each of the plurality of specially programmed processors accesses the circuit design data from the design database.

9. A system according to claim 1, wherein the managing computer processor and the specially programmed processors communicate via Ethernet.

10. A system according to claim 1, wherein the pixel-based bitmap representation of the integrated circuit comprises a plurality of pixels each having a pixel size, and wherein the pixel size is determined using a numerical aperture and wavelength of the lithographic process.

11. A system for performing a simulation of a lithographic process for fabricating an integrated circuit represented by circuit design data comprising a plurality of polygons, the system comprising:

a managing computer processor that converts the plurality of polygons in the circuit design data into a pixel-based bitmap representation of the integrated circuit;

a plurality of specially programmed computer processors, coupled to the managing computer processor, that each perform a respective portion of the simulation using the pixel-based bitmap representation of the integrated circuit, and wherein each of the plurality of specially programmed computer processors operates in parallel with the other specially programmed computer processors, and

wherein the managing computer combines the respective portions to form an overall result of the simulation.

12. A system according to claim 11, wherein the respective portions are respective areas of the pixel-based bitmap.

13. A system according to claim 12, wherein each of the plurality of specially programmed computer processors calculates a simulated aerial image corresponding to the respective area of the pixel-based bitmap.

14. A system according to claim 12, wherein each of the plurality of specially programmed computer processors calculates a simulated resist image corresponding to the respective area of the pixel-based bitmap.

15. A system according to claim 12, wherein the managing computer processor determines each respective portion performed by the plurality of specially programmed processors.

16. A system according to claim 11, wherein the circuit design data includes resolution enhancement technology.

17. A system according to claim 11, further comprising a design database for storing the circuit design data, wherein each of the plurality of specially programmed processors accesses the circuit design data from the design database.

18. A system according to claim 11, wherein the managing computer processor and the specially programmed processors communicate via Ethernet.