Displaying a congestion indicator for a channel in a circuit design layout

• US 8,893,073 B2
• Filed: 12/27/2012
• Issued: 11/18/2014
• Est. Priority Date: 12/27/2012
• Status: Active Grant

• Current Assignee: Synopsys Incorporated
• Original Assignee: Synopsys Incorporated
• Inventors: Rashingkar, Balkrishna R., Peart, David L., Segal, Russell, Chang, Douglas, Roze, Ksenia
• Primary Examiner(s): Kik, Phallaka
• Application Number:
  US13/728,873
• Publication Number:
  US 20140189617A1
• Time in Patent Office: 691 Days
• Field of Search: 716/139, 716/136, 716/106, 716/111, 716/122, 716/123, 716/129, 716/130, 703/15
• US Class Current: 716/139
• CPC Class Codes: G06F 2111/04 Constraint-based CAD
• CPC Class Codes: G06F 2111/12 Symbolic schematics
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/31 Design entry, e.g. editors specifically adapted for circuit design
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: G06F 30/3947 global
• CPC Class Codes: G06F 30/396 Clock trees
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

Methods and apparatuses are described for creating, editing, and viewing a floorplan of a circuit design. Specifically, some embodiments enable a user to perform a graphical operation at an inference point in a circuit design layout, wherein the location of the inference point is determined based on existing graphical objects in the circuit design layout. Some embodiments substantially instantaneously update a congestion indicator in a circuit design layout in response to modifying the circuit design layout. Some embodiments substantially instantaneously update pin locations of a block or partition in response to changing the size or shape of the block or partition. Some embodiments enable a user to view a circuit design layout based on the logical hierarchy, and also based on at least one additional attribute type such as voltage, power, or clock domain.

Claims

1. A method for displaying a congestion indicator for a channel in a circuit design layout, the method comprising:

displaying, in a graphical user interface (GUI), the congestion indicator for the channel;

modifying the circuit design layout based on user input to obtain a modified circuit design layout, wherein said modifying changes a width of the channel from a first width value to a second width value;

determining an updated capacity value for the channel based on the first and second width values, wherein the updated capacity value corresponds to an amount of available routing resources in the channel;

determining, by computer, an updated congestion indicator based on the updated capacity value; and

displaying, in the GUI, the updated congestion indicator for the channel.

2. The method of claim 1, wherein said displaying the updated congestion indicator comprises:

displaying a demand value that corresponds to a number of wires that are expected to be routed through the channel; and

displaying the updated capacity value.

3. The method of claim 1, wherein said displaying the updated congestion indicator comprises:

determining an updated color based on the updated capacity value; and

displaying a region in the circuit design layout that corresponds to the channel with the updated color.

4. The method of claim 1, wherein determining an updated capacity value for the channel comprises multiplying a capacity value of the channel by a ratio between the second and the first width values.

5. The method of claim 1, wherein the updated congestion indicator is determined without performing global routing on the modified circuit design layout.

6. A non-transitory computer-readable storage medium storing instructions that, when executed by a computer, cause the computer to perform a method for displaying a congestion indicator for a channel in a circuit design layout, the method comprising:

displaying, in a graphical user interface (GUI), the congestion indicator for the channel;

modifying the circuit design layout based on user input to obtain a modified circuit design layout, wherein said modifying changes a width of the channel to a second width value;

determining an updated capacity value for the channel based on the first and second width values, wherein the updated capacity value corresponds to an amount of available routing resources in the channel;

determining an updated congestion indicator based on the updated capacity value; and

displaying, in the GUI, the updated congestion indicator for the channel.

7. The non-transitory computer-readable storage medium of claim 6, wherein said displaying the updated congestion indicator comprises:

displaying a demand value that corresponds to a number of wires that are expected to be routed through the channel; and

displaying the updated capacity value.

8. The non-transitory computer-readable storage medium of claim 6, wherein said displaying the updated congestion indicator comprises:

determining an updated color based on the updated capacity value; and

displaying a region in the circuit design layout that corresponds to the channel with the updated color.

9. The non-transitory computer-readable storage medium of claim 6, wherein determining an updated capacity value for the channel comprises multiplying a capacity value of the channel by a ratio between the second and the first width values.

10. The non-transitory computer-readable storage medium of claim 6, wherein the updated congestion indicator is determined without performing global routing on the modified circuit design layout.

11. An apparatus, comprising:

a processor; and

a non-transitory computer-readable storage medium storing instructions that, when executed by the processor, cause the apparatus to perform a method for displaying a congestion indicator for a channel in a circuit design layout, the method comprising;

displaying, in a graphical user interface (GUI), the congestion indicator for the channel;

modifying the circuit design layout based on user input to obtain a modified circuit design layout, wherein said modifying changes a width of the channel from a first width value to a second width value;

determining an updated capacity value for the channel based on the first and second width values, wherein the updated capacity value corresponds to an amount of available routing resources in the channel;

determining an updated congestion indicator based on the updated capacity value; and

displaying, in the GUI, the updated congestion indicator for the channel.

12. The apparatus of claim 11, wherein said displaying the updated congestion indicator comprises:

displaying a demand value that corresponds to a number of wires that are expected to be routed through the channel; and

displaying the updated capacity value.

13. The apparatus of claim 11, wherein said displaying the updated congestion indicator comprises:

determining an updated color based on the updated capacity value; and

displaying a region in the circuit design layout that corresponds to the channel with the updated color.

14. The apparatus of claim 11, wherein determining an updated capacity value for the channel comprises multiplying a capacity value of the channel by a ratio between the second and the first width values.

15. The apparatus of claim 11, wherein the updated congestion indicator is determined without performing global routing on the modified circuit design layout.