Tipless transistors, short-tip transistors, and methods and circuits therefor

• US 8,895,327 B1
• Filed: 12/08/2012
• Issued: 11/25/2014
• Est. Priority Date: 12/09/2011
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: SuVolta, Inc.
• Inventors: Kidd, David A.
• Primary Examiner(s): HA, NATHAN W
• Application Number:
  US13/708,983
• Time in Patent Office: 717 Days
• Field of Search: 257/335, 257/355
• US Class Current: 438/17
• CPC Class Codes: G11C 7/065 Differential amplifiers of latching type
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1041 with a non-uniform doping structure in the channel region surface
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/365 Planar doping, e.g. atomic-plane doping, delta-doping
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 3/356 Bistable circuits
• CPC Class Codes: H03K 3/356113 using additional transistors in the input circuit
• CPC Class Codes: H03K 3/356121 with synchronous operation H03K3/35613, H03K3/356147 take precedence
• CPC Class Codes: H03K 5/05 by the use of clock signals or other time reference signals
• CPC Class Codes: H03K 5/06 by the use of delay lines or other analogue delay elements
• CPC Class Codes: H03L 7/08 Details of the phase-locked loop
• CPC Class Codes: H03L 7/081 : provided with an additional controlled phase shifter H03L7/0998 takes precedence

Abstract

An integrated circuit can include a plurality of first transistors formed in a substrate and having gate lengths of less than one micron; and at least one tipless transistor formed in the substrate and having a source-drain path coupled between a circuit node and a first power supply voltage; wherein at least one tipless transistor has source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode. In addition or alternatively, an integrated circuit can include minimum feature size transistors having gate lengths of less than one micron; a signal driving circuit comprising a first transistor of a first conductivity type having a source-drain path coupled between a first power supply node and an output node, and a second transistor of a second conductivity type having a source-drain path coupled between a second power supply node and the output node, and a gate coupled to a gate of the first transistor, wherein at least one of the first or second transistor is a tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode.

Claims

1. A method, comprising:

receiving input signals to generate at least one output signal with a plurality of transistors, including transistors having gate lengths of less than one micron; and

driving at least one signal with a driver circuit that includes at least one tipless transistor by replacing a first driver circuit that does not include tipless transistors with a second driver circuit that includes at least one tipless transistor, the at least one tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode, wherein the second driver circuit has a longer signal propagation delay than the first driver circuit.

2. The method of claim 1, wherein:

the at least one tipless transistor is a deeply depleted channel (DDC) transistor having a source and drain doped to one conductivity type, a substantially undoped channel region, and a highly doped screening region of another conductivity type formed below the channel region.

3. The method of claim 1, wherein:

generating at least one output signal includes generating the at least one output signal with first transistors having controllable source-drain current paths coupled between a first and second node, the first transistors having a source drain doping profile with extension regions that extend in a lateral direction under a gate electrode of the first transistors, the first transistors being formed in a substrate and having drawn gate lengths of less than one micron; and

the at least one tipless transistor having a drawn gate length of less than one micron.

4. The method of claim 3, wherein:

the first transistors comprise deeply depleted channel (DDC) transistors having a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the second conductivity type formed below the channel region.

5. The method of claim 1, wherein:

the at least one tipless transistor comprises a deeply depleted channel (DDC) transistor having a source and drain doped to a first conductivity type, a substantially undoped channel region, and a highly doped screening region of the second conductivity type formed below the channel region.

6. The method of claim 1, wherein:

the at least one tipless transistor is a conventional MOSFET having a source drain vertical doping profile without extension regions that extend in a lateral direction under a gate electrode of the tipless transistor.

7. The method of claim 1, further including:

delaying the at least one signal with a delay circuit to generate a delayed signal, the delay circuit comprising at least one delay tipless transistor, the delay the tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode.

8. The method of claim 7, further including:

logically combining signals at a plurality of gate inputs to generate a gate output signal;

wherein

one of the combined signals is the at least one signal and another of the combined signals is the delayed signal.

9. The method of claim 7, further including:

latching the delayed signal with at least one flip-flop circuit.

10. The method of claim 7, further including:

receiving input signals to generate at least one output signal includes generating an initial sense amplifier control signal from memory device input signals;

delaying the at least one signal includes delaying the initial sense amplifier control signal to generate a delayed sense amplifier signal; and

amplifying signals from memory cells of a memory cell array with sense amplifiers in response to the delayed sense amplifier signal.

11. The method of claim 7, wherein:

delaying the at least one signal includes delaying a periodic timing clock to generate a delayed periodic timing clock.

12. The method of claim 7, wherein:

the delay circuit is selected from;

a phase locked loop circuit and a delay locked loop circuit.

13. The method of claim 1, wherein:

the plurality of transistors have drawn gate lengths of less than 0.5 micron; and

the at least one tipless transistor has a drawn gate length of less than 0.5 micron.

14. A method, comprising:

receiving input signals to generate at least one output signal with a plurality of transistors, including transistors having gate lengths of less than one micron;

driving at least one signal with a driver circuit that includes at least one tipless transistor, the tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode; and

delaying the at least one signal with a delay circuit to generate a delayed signal, the delay circuit comprising at least one delay tipless transistor, the delay the tipless transistor having source and drain vertical doping profiles without extension regions that extend in a lateral direction under a gate electrode.

15. The method of claim 14, further including:

logically combining signals at a plurality of gate inputs to generate a gate output signal;

wherein

one of the combined signals is the at least one signal and another of the combined signals is the delayed signal.

16. The method of claim 15, wherein:

logically combining the signals to generate a pulse having a duration that includes the delay introduced by the delay circuit.

17. The method of claim 14, further including:

latching the delayed signal with at least one flip-flop circuit.

18. The method of claim 14, further including:

receiving input signals to generate at least one output signal includes generating an initial sense amplifier control signal from memory device input signals;

delaying the at least one signal includes delaying initial sense amplifier control signal to generate a delayed sense amplifier signal; and

amplifying signals from memory cells of a memory cell array with sense amplifiers in response to the delayed sense amplifier signal.

19. The method of claim 14, wherein:

delaying the at least one signal includes delaying a periodic timing clock to generate a delayed periodic timing clock.

20. The method of claim 14, wherein:

the delay circuit is selected from;

a phase locked loop circuit and a delay locked loop circuit.