Trench FET with source recess etch

• US 8,895,394 B2
• Filed: 06/20/2012
• Issued: 11/25/2014
• Est. Priority Date: 06/20/2012
• Status: Active Grant

• Current Assignee: NXP USA, Inc. (NXP Semiconductors NV)
• Original Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Inventors: Qin, Ganming, de Frsart, Edouard D., Wang, Peilin, Ku, Pon S.
• Primary Examiner(s): Rizkallah, Kimberly
• Assistant Examiner(s): Ligai, Maria
• Application Number:
  US13/528,375
• Publication Number:
  US 20130344667A1
• Time in Patent Office: 888 Days
• Field of Search: 257/330, 257/332, 257/333, 257/E21.419, 438/270, 438/272, 438/273
• US Class Current: 438/272
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A high voltage vertical field effect transistor device (101) is fabricated in a substrate (102, 104) using angled implantations (116, 120) into trench sidewalls formed above recessed gate poly layers (114) to form self-aligned N+ regions (123) adjacent to the trenches and along an upper region of an elevated substrate. With a trench fill insulator layer (124) formed over the recessed gate poly layers (114), self-aligned P+ body contact regions (128) are implanted into the elevated substrate without counter-doping the self-aligned N+ regions (123), and a subsequent recess etch removes the elevated substrate, leaving self-aligned N+ source regions (135-142) and P+ body contact regions (130-134).

Claims

1. A method for fabricating a vertical field effect transistor, comprising:

forming a recessed conductive gate electrode structure in a trench opening of a semiconductor substrate structure, the recessed conductive gate structure having a top surface which is below an elevated surface region of the semiconductor substrate structure;

forming an implant block layer over the recessed conductive gate electrode structure in the trench opening by depositing an oxide layer to fill the portion of the trench opening above the recessed conductive gate electrode structure and planarizing the oxide layer to form an oxide implant block layer over the recessed conductive gate electrode structure in the trench opening;

implanting dopants of a first conductivity type using one or more angled implants into an upper region of an elevated substrate and trench sidewalls located above the recessed conductive gate electrode structure to form surface implant regions and self-aligned source regions adjacent to the recessed conductive gate electrode structure;

implanting dopants of a second opposite conductivity type into the semiconductor substrate structure to form self-aligned body contact regions adjacent to the self-aligned source regions;

applying a recess etch to the elevated surface region of the semiconductor substrate structure to remove the surface implant region while retaining the self-aligned source regions adjacent to the recessed conductive gate electrode structure and the self-aligned body contact regions adjacent to the self-aligned source regions; and

applying a recess etch to the implant block layer after applying the recess etch to the elevated surface region of the semiconductor substrate structure, thereby forming a recessed implant block layer that is substantially coplanar with the self-aligned body contact regions and self-aligned source regions.

2. The method of claim 1, where implanting dopants of the first conductivity type comprises using one or more angled implants without using an implant mask to form first surface implant regions in the elevated surface region of the semiconductor substrate structure and first sidewall implant regions in the first and second opposite trench sidewalls that extend to a first depth that is below the top surface of the recessed conductive gate electrode structure.

3. The method of claim 1, where implanting dopants of the second opposite conductivity type comprises implanting dopants of a second opposite conductivity type into the semiconductor substrate structure without using an implant mask to form self-aligned body contact regions adjacent to the self-aligned source regions.

4. The method of claim 1, further comprising implanting dopants of the second opposite conductivity type into the semiconductor substrate structure to form body regions to a depth that is substantially equal to the depth of the trench opening.

5. The method of claim 1, where implanting dopants of the second opposite conductivity type forms self-aligned body contact regions to a depth that is substantially equal to the depth of the self-aligned source regions adjacent to the recessed conductive gate electrode structure.

6. The method of claim 1, where applying the recess etch to the elevated surface region of the semiconductor substrate structure comprises applying a chemical mechanical polish or reactive ion etch process to the elevated surface region of the semiconductor substrate structure.

7. The method of claim 1, further comprising forming a conductive metal conductor layer to electrically contact the self-aligned body contact regions and self-aligned source regions, either directly or indirectly through one or more silicide layers.

8. A method for fabricating a trench field effect transistor, comprising:

providing a semiconductor substrate structure having an elevated surface region;

forming a plurality of trench openings in the semiconductor substrate structure, where each trench opening is defined by first and second opposite trench sidewalls;

forming a recessed conductive gate electrode structure in each trench opening, the recessed conductive gate structure having a top surface which is below the elevated surface region of the semiconductor substrate structure;

forming an implant block layer over the recessed conductive gate electrode structure in each trench opening by depositing an oxide layer to fill the plurality of trench openings above the recessed conductive gate electrode structures and planarizing the oxide layer to form an oxide implant block layer over each recessed conductive gate electrode structure;

implanting dopants of a first conductivity type using one or more angled implants to form first surface implant regions in the elevated surface region of the semiconductor substrate structure and first sidewall implant regions in the first and second opposite trench sidewalls of each trench opening that extend to a first depth that is below the top surface of the recessed conductive gate electrode structure;

implanting dopants of a second opposite conductivity type to form second implant regions between each trench opening in the semiconductor substrate structure to a second depth that penetrates below the elevated surface region of the semiconductor substrate;

recessing the elevated surface region of the semiconductor substrate structure to remove the first surface implant regions and part of the second implant regions while leaving at least part of the first sidewall implant regions in the first and second opposite trench sidewalls and a part of the second implant regions in the recessed semiconductor substrate structure; and

applying a recess etch to the implant block layer in each trench opening, thereby forming a recessed implant block layer that is substantially coplanar with the first sidewall implant regions remaining after recessing the elevated surface region.

9. The method of claim 8, where implanting dopants of the first conductivity type comprises using one or more angled implants which impinge at an incident angle of between about 30-45 degrees to the elevated surface region of the substrate structure.

10. The method of claim 8, where forming the recessed conductive gate electrode structure comprises:

forming a gate dielectric layer in the plurality of trench openings;

depositing a conformal layer of polysilicon over the gate dielectric layer in the plurality of trench openings;

applying a reactive ion etch to etch the conformal layer of polysilicon to have a top surface which is below an elevated surface region of the semiconductor substrate structure.

11. The method of claim 8, where forming the plurality of trench openings comprises:

forming patterned nitride layer and oxide layer on the elevated surface region of the semiconductor substrate defining a plurality of etch openings over the intended trench openings;

selectively removing portions of the semiconductor substrate structure exposed by the plurality of etch openings to form the plurality of trench openings in the semiconductor substrate structure; and

stripping the patterned nitride layer prior to implanting dopants of the first conductivity type.

12. The method of claim 8, further comprising implanting dopants of the second opposite conductivity type into the semiconductor substrate structure to form body regions between the plurality of trench openings to a depth that is substantially equal to the depth of the plurality of trench openings, where the body regions have an implant dose that is lower than the first surface implant regions and first sidewall implant regions.

13. The method of claim 8, where implanting dopants of the second opposite conductivity type comprises implanting dopants of the second opposite conductivity type using an implant dose that is lower than the first surface implant regions and first sidewall implant regions to form self-aligned body contact regions to a depth that is substantially equal to the depth of the first sidewall implant regions.

14. The method of claim 8, where recessing the elevated surface region comprises applying a chemical mechanical polish or reactive ion etch process to the elevated surface region of the semiconductor substrate structure.

15. A method of forming a trench transistor, comprising:

a) forming a trench in a substrate, the substrate having a surface and the trench having a first upper sidewall and a second upper sidewall;

b) forming a recessed gate structure in the trench, the recessed gate structure having a top surface which is below the surface of the substrate to thereby expose the first and second upper sidewalls;

c) forming an implant block layer over the recessed gate structure in the trench by depositing an oxide layer to fill the trench above the recessed gate structure and planarizing the oxide layer to form an oxide implant block layer over the recessed gate structure;

d) implanting a first dose of dopants such that a portion of the first dose is implanted through the first upper sidewall to form first self-aligned source regions, and a further portion of the first dose is implanted through the surface to form a first surface implant region;

e) changing an orientation of the substrate relative to an axis of implantation by a predetermined number of degrees;

f) implanting a second dose of dopants such that a portion of the second dose is implanted through the second upper sidewall to form second self-aligned source regions, and a further portion of the second dose is implanted through the surface to form a second surface implant region;

g) implanting a third dose of dopants into the substrate without using an implant mask to form a self-aligned body contact regions adjacent to the first and second self-aligned source regions;

h) applying a recess etch to the substrate to remove the first and second surface implant region while retaining portions of the first and second self-aligned source regions adjacent to the recessed gate structure and the self-aligned body contact region; and

i) applying a recess etch to the implant block layer in the trench, thereby forming a recessed implant block layer that is substantially coplanar with the first and second self-aligned source regions remaining after applying the recess etch to the substrate.

16. The method of claim 15, further comprising forming a conductive metal conductor layer to electrically contact the portions of the first and second self-aligned source regions and the self-aligned body contact regions, either directly or indirectly through one or more silicide layers.