Reduced resistance SiGe FinFET devices and method of forming same
First Claim
1. A method for forming a fin field-effect transistor (FinFET) device, the method comprising:
- forming a plurality of silicon fins on a substrate;
depositing silicon germanium (SiGe) on the plurality of fins;
forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe;
removing the SiGe from an area of the fins not covered by the dummy gate stack;
forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region;
removing the dummy gate stack to expose the remaining SiGe in the gate region;
mixing the SiGe with the silicon fins in the gate region to form SiGe fins; and
depositing a gate dielectric and gate metal on the SiGe fins.
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Abstract
A method for forming a fin field-effect transistor (FinFET) device, comprises forming a plurality of silicon fins on a substrate, depositing silicon germanium (SiGe) on the plurality of fins, forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe, removing the SiGe from an area of the fins not covered by the dummy gate stack, forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region, removing the dummy gate stack to expose the remaining SiGe in the gate region, mixing the SiGe with the silicon fins in the gate region to form SiGe fins, and depositing a gate dielectric and gate metal on the SiGe fins.
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Citations
15 Claims
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1. A method for forming a fin field-effect transistor (FinFET) device, the method comprising:
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forming a plurality of silicon fins on a substrate; depositing silicon germanium (SiGe) on the plurality of fins; forming a gate region by forming a dummy gate stack on a predetermined area of the fins including the SiGe; removing the SiGe from an area of the fins not covered by the dummy gate stack; forming a merged region in the area of the fins not covered by the dummy gate stack to form a source drain region; removing the dummy gate stack to expose the remaining SiGe in the gate region; mixing the SiGe with the silicon fins in the gate region to form SiGe fins; and depositing a gate dielectric and gate metal on the SiGe fins. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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Specification