Epitaxial Process of forming stress inducing epitaxial layers in source and drain regions of PMOS and NMOS structures

• US 8,895,396 B1
• Filed: 07/11/2013
• Issued: 11/25/2014
• Est. Priority Date: 07/11/2013
• Status: Active Grant

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Fu, Ssu-I, Hung, Yu-Hsiang, Chen, Cheng-Guo, Chang, Chung-Fu, Lin, Chien-Ting
• Primary Examiner(s): Garber, Charles
• Assistant Examiner(s): PATERSON, BRIGITTE A
• Application Number:
  US13/940,220
• Time in Patent Office: 502 Days
• Field of Search: None
• US Class Current: 438/278
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6653 using the removal of at least part of spacer, e.g. disposable spacer
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain

Abstract

An epitaxial process includes the following steps. A first gate and a second gate are formed on a substrate. Two first spacers are formed on the substrate beside the first gate and the second gate respectively. Two first epitaxial layers having first profiles are formed in the substrate beside the two first spacers respectively. A second spacer material is formed to cover the first gate and the second gate. The second spacer material covering the second gate is etched to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate. The exposed first epitaxial layer in the substrate beside the second spacer is replaced by a second epitaxial layer having a second profile different from the first profile.

Claims

1. An epitaxial process, comprising:

forming a first gate and a second gate on a substrate;

forming two first spacers on the substrate beside the first gate and the second gate respectively;

forming two first epitaxial layers having first profiles in the substrate beside the two first spacers respectively;

forming a second spacer material covering the first gate and the second gate;

etching the second spacer material covering the second gate to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate; and

replacing the exposed first epitaxial layer in the substrate beside the second spacer by a second epitaxial layer having a second profile different from the first profile, wherein the first epitaxial layers comprise bottom buffer layers, and the bottom buffer layer of the exposed first epitaxial layer remains while the exposed first epitaxial layer is replaced by the second epitaxial layer to serve as a bottom buffer layer of the second epitaxial layer.

2. The epitaxial process according to claim 1, wherein the step of forming the two first spacers comprises:

forming a first spacer material covering the first gate and the second gate; and

etching the first spacer material to form the two first spacers on the substrate beside the first gate and the second gate respectively.

3. The epitaxial process according to claim 1, wherein the heights of the first epitaxial layers are different from the height of the second epitaxial layer.

4. The epitaxial process according to claim 1, wherein the first epitaxial layers comprise silicon phosphorous epitaxial layers.

5. The epitaxial process according to claim 1, wherein the second epitaxial layer comprises a silicon germanium epitaxial layer.

6. The epitaxial process according to claim 1, further comprising:

forming two first recesses having the first profiles in the substrate beside the first gate and the second gate respectively for the two first epitaxial layers to be formed therein after the two first spacers are formed.

7. The epitaxial process according to claim 1, wherein the first spacers and the second spacer comprise materials having etching selectivity.

8. The epitaxial process according to claim 1, wherein the second spacer has an etching rate higher than that of the first spacers.

9. The epitaxial process according to claim 1, wherein the first spacers and the second spacer comprise nitride spacers with different etching rates.

10. The epitaxial process according to claim 1, wherein the first spacers and the second spacer have different materials.

11. The epitaxial process according to claim 1, wherein the step of forming the second spacer comprises:

forming a patterned photoresist on the first gate and the substrate beside the first gate;

etching the exposed second spacer material covering the second gate while reserving the unexposed second spacer material covering the first gate to form the second spacer; and

removing the patterned photoresist.

12. The epitaxial process according to claim 1, further comprising:

forming a second recess having the second profile in the substrate beside the second gate for the second epitaxial layer to be formed therein after the second spacer is formed.

13. The epitaxial process according to claim 12, wherein the step of replacing the exposed first epitaxial layer in the substrate beside the second spacer by the second epitaxial layer comprises:

removing the exposed first epitaxial layer and forming the second recess in the substrate beside the second spacer; and

forming the second epitaxial layer in the second recess.

14. The epitaxial process according to claim 13, wherein the first epitaxial layer is removed and the second recess is formed during the same process.

15. The epitaxial process according to claim 13, wherein the steps of forming the second spacer and removing the first epitaxial layer are performed during the same process.

16. The epitaxial process according to claim 1, wherein the first profile has a U-shaped cross-sectional profile while the second profile has a diamond-shaped cross-sectional profile.

17. The epitaxial process according to claim 1, wherein the distance between the first epitaxial layer and the first gate is shorter than the distance between the second epitaxial layer and the second gate.

18. An epitaxial process, comprising:

forming a first gate and a second gate on a substrate;

forming two first spacers on the substrate beside the first gate and the second gate respectively;

forming two first epitaxial layers having first profiles in the substrate beside the two first spacers respectively;

forming a second spacer material covering the first gate and the second gate;

etching the second spacer material covering the second gate to form a second spacer on the substrate beside the second gate and expose the first epitaxial layer beside the second spacer while reserving the second spacer material covering the first gate; and

replacing the exposed first epitaxial layer in the substrate beside the second spacer by a second epitaxial layer having a second profile different from the first profile, wherein the minimum distance between the second epitaxial layers beside the second gate is shorter than the minimum distance between the first epitaxial layers beside the first gate.