Fin deformation modulation

• US 8,895,446 B2
• Filed: 02/18/2013
• Issued: 11/25/2014
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Peng, Chih-Tang, Huang, Tai-Chun, Lien, Hao-Ming
• Primary Examiner(s): Nhu, David
• Application Number:
  US13/769,783
• Publication Number:
  US 20140231919A1
• Time in Patent Office: 645 Days
• Field of Search: 438/270, 438/700, 438/311, 438/502, 438/552, 438/587, 438/513, 438/680, 438/692, 438/679, 438/769, 438/706, 438/745, 257/E21.006, 257/E21.014, 257/E21.027, 257/E21.058, 257/E21.077, 257/E21.17, 257/E21.227, 257/E21.229, 257/E21.244, 257/E21.267, 257/E21.304, 257/E21.311, 257/E21.546
• US Class Current: 438/700
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76229 Concurrent filling of a plurality of trenches having a different trench shape or dimension, e.g. rectangular and V-shaped trenches, wide and narrow trenches, shallow and deep trenches
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/845 including field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method includes forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches. The plurality of trenches includes a first trench and second trench wider than the first trench. A first dielectric material is filled in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially. A second dielectric material is formed over the first dielectric material. The second dielectric material fills an upper portion of the second trench, and has a shrinkage rate different from the first shrinkage rate of the first dielectric material. A planarization is performed to remove excess second dielectric material. The remaining portions of the first dielectric material and the second dielectric material form a first and a second STI region in the first and the second trenches, respectively.

Claims

1. A method of manufacturing semiconductor fins and Fin Field Effect Transistors (FinFETs), the method comprising:

forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches, wherein the plurality of trenches comprises a first trench and second trench wider than the first trench;

filling a first dielectric material in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially, and wherein the first dielectric material has a first shrinkage rate;

forming a second dielectric material over the first dielectric material, wherein the second dielectric material fills an upper portion of the second trench, and wherein the second dielectric material has a second shrinkage rate different from the first shrinkage rate; and

performing a planarization to remove excess portions of the second dielectric material over the semiconductor substrate, wherein remaining portions of the first dielectric material and the second dielectric material form a first and a second Shallow Trench Isolation (STI) regions in the first and the second trenches, respectively.

2. The method of claim 1, wherein the first shrinkage rate is greater than the second shrinkage rate.

3. The method of claim 1 further comprising, after the step of filling the first dielectric material and before forming the second dielectric material, performing an anneal on the first dielectric material.

4. The method of claim 1 further comprising, after the planarization, performing an annealing, wherein the semiconductor strips between the plurality of trenches are partially oxidized to have a volume expansion, and wherein the volume expansion substantially compensates for a shrinkage of the first and the second dielectric materials.

5. The method of claim 1, wherein the first dielectric material is flowable when filled, and the second dielectric material is non-flowable when formed.

6. The method of claim 1 further comprising, after the planarization:

recessing the first and the second dielectric materials to form recesses, wherein portions of the semiconductor strips over top surfaces of remaining portions of the first and the second dielectric materials form semiconductor fins, wherein after the step of recessing, the STI region comprises the first dielectric material, and is free from the second dielectric material, and the second STI region comprises the first and the second dielectric materials.

7. The method of claim 6 further comprising:

forming a gate dielectric on sidewalls and top surface of the semiconductor fins; and

forming a gate electrode over the gate dielectric.

8. A method of manufacturing semiconductor fins and Fin Field Effect Transistors (FinFETs), the method comprising:

forming a plurality of trenches extending from a top surface of a semiconductor substrate into the semiconductor substrate, with semiconductor strips formed between the plurality of trenches, wherein the plurality of trenches comprises a first trench and second trench wider than the first trench;

filling a first dielectric material in the plurality of trenches, wherein the first trench is substantially fully filled, and the second trench is filled partially;

performing a first anneal on the first dielectric material;

after the first anneal, filling a second dielectric material over the first dielectric material, wherein the second dielectric material fully fills the second trench; and

performing a planarization to remove excess portions of the second dielectric material over the semiconductor substrate, wherein remaining portions of the first dielectric material and the second dielectric material form Shallow Trench Isolation (STI) regions.

9. The method of claim 8, wherein the first dielectric material and the second dielectric material are different from each other.

10. The method of claim 9, wherein the first dielectric material has a first shrinkage rate, and wherein the second dielectric material has a second shrinkage rate smaller than the first shrinkage rate.

11. The method of claim 8 further comprising, after the planarization, performing a second anneal, wherein the semiconductor strips are partially oxidized.

12. The method of claim 11, wherein after the first anneal and before the step of filling the second dielectric material, the semiconductor strips are bended, and wherein after the second anneal, the semiconductor strips are substantially straightened.

13. The method of claim 8, wherein the first dielectric material is flowable when filled, and the second dielectric material is non-flowable when filled.

14. The method of claim 8, further comprising, after the planarization:

recessing the first and the second dielectric materials to form recesses, wherein portions of the semiconductor strips over top surfaces of remaining portions of the first and the second dielectric materials form semiconductor fins, and wherein after recessing, a first one of the STI regions in the first trench comprises the first dielectric material, and is free from the second dielectric material, and a second one of the STI regions in the second trench comprises the first and the second dielectric materials.

15. The method of claim 14, further comprising:

forming a gate dielectric on sidewalls and top surface of the semiconductor fins; and

forming a gate electrode over the gate dielectric.

16. A method of making semiconductor strips and Shallow Trench Isolation (STI) regions, the method comprising:

etching a semiconductor substrate to form a plurality of trenches in the semiconductor substrate;

filling a first dielectric material into the plurality of trenches;

solidifying the first dielectric material;

filling a second dielectric material into the plurality of trenches after the solidifying the first dielectric material;

solidifying the second dielectric material; and

performing a planarization to remove excess portions of the second dielectric material, wherein remaining portions of the first dielectric material and the second dielectric material form Shallow Trench Isolation (STI) regions in the plurality of trenches.

17. The method of claim 16, wherein a first one of the plurality of trenches is substantially fully filled by the first dielectric material, and wherein a second one of the plurality of trenches is filled with the first dielectric material and the second dielectric material.

18. The method of claim 17, wherein the first one of the plurality of trenches is narrower than the second one of the plurality of trenches.

19. The method of claim 16, wherein after the solidifying the first dielectric material and before the filling the second dielectric material, semiconductor strips between the plurality of trenches are bended, and wherein after the solidifying the second dielectric material, the semiconductor strips are substantially straightened.

20. The method of claim 16, wherein the first dielectric material is flowable when filled, and the second dielectric material is non-flowable when filled.