Termination arrangement for vertical MOSFET
First Claim
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1. A transistor device comprising:
- an active region, including at least one vertical channel transistor cell, and a termination region electrically coupled to the active region;
a semiconductor layer disposed at the active region and the termination region;
a gate insulator layer disposed partly on a portion of the vertical channel transistor cell and partly on a portion of the semiconductor layer at the termination region; and
a field insulator layer disposed on another portion of the semiconductor layer at the termination region and forming a step structure on the other portion of the semiconductor layer at the termination region, the step structure of the field insulator layer being formed as a thickening of the field insulator layer from a first thickness to a second thickness, the first thickness being less than the second thickness.
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Accused Products
Abstract
Representative implementations of devices and techniques provide a termination arrangement for a transistor structure. The periphery of a transistor structure may include a recessed area having features arranged to improve performance of the transistor at or near breakdown.
7 Citations
13 Claims
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1. A transistor device comprising:
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an active region, including at least one vertical channel transistor cell, and a termination region electrically coupled to the active region; a semiconductor layer disposed at the active region and the termination region; a gate insulator layer disposed partly on a portion of the vertical channel transistor cell and partly on a portion of the semiconductor layer at the termination region; and a field insulator layer disposed on another portion of the semiconductor layer at the termination region and forming a step structure on the other portion of the semiconductor layer at the termination region, the step structure of the field insulator layer being formed as a thickening of the field insulator layer from a first thickness to a second thickness, the first thickness being less than the second thickness. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A transistor structure comprising:
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a matrix of transistor cells, each transistor cell having a body layer, a trench, and a gate portion disposed in the trench; a termination region arranged at a periphery of the matrix of transistor cells, the termination region comprising a recessed trough; a field insulator portion disposed over the recessed trough at the termination region and forming an insulator step; a deep body portion embedded in the recessed trough at the termination region and electrically coupled to at least one of the transistor cells at the periphery of the matrix of transistor cells; and a semiconductor field plate structure disposed over the insulator step. - View Dependent Claims (9, 10, 11, 12)
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13. A metal-oxide-semiconductor field-effect transistor (MOSFET) device, comprising:
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an active region including a first plurality of transistor cells, each of the first plurality of transistor cells having a source region, a trench, and a gate structure disposed in the trench; a termination region including a second plurality of transistor cells arranged at a periphery of the active region and having electrical connectivity with one or more transistor cells of the first plurality of transistor cells, the transistor cells of the second plurality of transistor cells having a width substantially equal to a width of the transistor cells of the first plurality of transistor cells; a deep body region coupled to one or more transistor cells of the second plurality of transistor cells and located at a recessed trough at a periphery of the termination region; a gate oxide/field oxide step structure disposed over a preselected portion of the implanted deep body; and a semiconductor field plate structure disposed over the field oxide step structure and the implanted deep body.
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Specification