Trench power MOSFET

• US 8,896,060 B2
• Filed: 06/01/2012
• Issued: 11/25/2014
• Est. Priority Date: 06/01/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Ng, Chun-Wai, Chou, Hsueh-Liang, Liu, Ruey-Hsin, Su, Po-Chih
• Primary Examiner(s): Lee, Cheung
• Assistant Examiner(s): BRADLEY, STEPHEN M
• Application Number:
  US13/486,681
• Publication Number:
  US 20130320435A1
• Time in Patent Office: 907 Days
• Field of Search: 257330-335, 438/259
• US Class Current: 257/332
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/4916 the conductor material next to the insulator being a silicon layer, e.g. polysilicon doped with boron, phosphorus or nitrogen H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/495 the conductor material next to the insulator being a simple metal, e.g. W, Mo H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A device includes a semiconductor region of a first conductivity type, a trench extending into the semiconductor region, and a conductive field plate in the trench. A first dielectric layer separates a bottom and sidewalls of the field plate from the semiconductor region. A main gate is disposed in the trench and overlapping the field plate. A second dielectric layer is disposed between and separating the main gate and the field plate from each other. A Doped Drain (DD) region of the first conductivity type is under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region. A body region includes a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

Claims

1. A device comprising:

a semiconductor region of a first conductivity type;

a trench extending into the semiconductor region;

a field plate in the trench, wherein the field plate is conductive;

a first dielectric layer separating a bottom and sidewalls of the field plate from the semiconductor region;

a main gate in the trench and overlapping the field plate;

a second dielectric layer between and separating the main gate and the field plate from each other, wherein the second dielectric layer comprises a bottom surface;

a Doped Drain (DD) region of the first conductivity type under the second dielectric layer, wherein an edge portion of the main gate overlaps the DD region, and the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer; and

a body region comprising a first portion at a same level as a portion of the main gate, and a second portion underlying and contacting the bottom surface of the second dielectric layer, wherein the body region is of a second conductivity type opposite the first conductivity type.

2. The device of claim 1, wherein the main gate, the DD region and the body region form a power Metal-oxide-Semiconductor Field Effect Transistor (MOSFET), and wherein the power MOSFET comprises a source over the body region, and a drain underlying the semiconductor region.

3. The device of claim 1, wherein the semiconductor region has an impurity concentration lower than an impurity concentration of the DD region.

4. The device of claim 1, wherein the DD region comprises an inner sidewall contacting a sidewall portion of the first dielectric layer, and wherein the semiconductor region comprises a portion level with, and contacting an outer sidewall of the DD region.

5. The device of claim 1, wherein the second dielectric layer comprises:

a bottom surface contacting a top surface of the DD region; and

a top surface contacting a bottom surface of the main gate.

6. The device of claim 1, wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer.

7. The device of claim 1, wherein the DD region has a bottom surface higher than a bottom surface of the field plate.

8. A device comprising:

a semiconductor region of a first conductivity type selected from the group consisting essentially of p-type and n-type;

a trench extending from a top surface of the semiconductor region into the semiconductor region;

a first dielectric layer lining a bottom and sidewalls of the trench;

a field plate comprising a bottom and sidewalls contacting the first dielectric layer,

wherein the field plate is conductive;

a main gate in the trench and overlapping the field plate;

a second dielectric layer between and separating the main gate and the field plate from each other; and

a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer.

9. The device of claim 8, wherein an edge portion of the main gate overlaps the DD region.

10. The device of claim 8 further comprising a body region comprising a first portion at a same level as a portion of the main gate, and a second portion overlapped by a portion of the first dielectric layer, with the portion of the first dielectric layer being below the main gate, wherein the body region is of a second conductivity type opposite the first conductivity type.

11. The device of claim 8, wherein the main gate and the DD region form parts of a power Metal-oxide-Semiconductor Field Effect Transistor (MOSFET), and wherein the power MOSFET comprises a source over the main gate, and a drain underlying semiconductor region.

12. The device of claim 8, wherein the power MOSFET further comprises a heavily doped region of the first conductivity type between the semiconductor region and the drain.

13. The device of claim 8, wherein the DD region has a bottom surface higher than a bottom surface of the field plate.

14. A device comprising:

a semiconductor region of a first conductivity type;

a trench extending from a top surface of the semiconductor region into the semiconductor region;

a first dielectric layer lining a bottom and sidewalls of the trench;

a field plate comprising a bottom and sidewalls contacting the first dielectric layer, wherein the field plate is conductive;

a second dielectric layer over and contacting the field plate;

a Doped Drain (DD) region of the first conductivity type, wherein the DD region comprises a top surface contacting a substantially horizontal bottom surface of the second dielectric layer, and a sidewall contacting the first dielectric layer, wherein the DD region has an impurity concentration greater than an impurity concentration of the semiconductor region; and

a main gate in the trench, wherein an edge portion of the main gate overlaps the DD region, wherein the second dielectric layer is between and separates the main gate and the field plate from each other, and wherein the main gate comprises a distinguishable vertical interface substantially aligned to an interface between the DD region and the first dielectric layer.

15. The device of claim 14, wherein the main gate overlaps the field plate.

16. The device of claim 14 further comprising a body region comprising a first portion at a same level as a portion of the main gate, and a second portion at a same level as, and contacting, the DD region, wherein the body region is of a second conductivity type opposite the first conductivity type.

17. The device of claim 14, wherein the main gate and the DD region form parts of a power Metal-oxide-Semiconductor Field Effect Transistor (MOSFET), and wherein the power MOSFET comprises a source over the main gate, and a drain underlying semiconductor region.

18. The device of claim 14, wherein the power MOSFET further comprises a heavily doped region of the first conductivity type between the semiconductor region and the drain.

19. The device of claim 14, wherein the DD region has a bottom surface higher than a bottom surface of the field plate.