Interposers for semiconductor devices and methods of manufacture thereof

• US 8,896,089 B2
• Filed: 11/09/2011
• Issued: 11/25/2014
• Est. Priority Date: 11/09/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chiu, Tzu-Wei, Wang, Tzu-Yu, Wu, Wei-Cheng, Liu, Chun-Yi, Hu, Hsien-Pin, Hou, Shang-Yun
• Primary Examiner(s): Luke, Daniel
• Assistant Examiner(s): Ahmad, Khaja
• Application Number:
  US13/292,792
• Publication Number:
  US 20130113070A1
• Time in Patent Office: 1,112 Days
• Field of Search: 257/209, 257/529, 257/530, 257/698, 257/E23.147, 257/E23.149, 257/E21.592, 438131-132, 438/600, 438/467
• US Class Current: 257/529
• CPC Class Codes: H01L 2224/13124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/13169 Platinum [Pt] as principal constituent
• CPC Class Codes: H01L 2224/13184 Tungsten [W] as principal constituent
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2224/81192 wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/81805 involving forming a eutectic alloy at the bonding interface
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5256 comprising fuses, i.e. connections having their state changed from conductive to non-conductive
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 24/81 : using a bump connector
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00011 : Not relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/157 : with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof

Abstract

Interposers for semiconductor devices and methods of manufacture thereof are disclosed. In one embodiment, an interposer includes a substrate, a contact pad disposed on the substrate, and a first through-via in the substrate coupled to the contact pad. A first fuse is coupled to the first through-via. A second through-via in the substrate is coupled to the contact pad, and a second fuse is coupled to the second through-via.

Claims

1. An interposer, comprising:

a substrate;

a contact pad disposed on a first side of the substrate;

a first through-via in the substrate having a first end terminating on and directly contacting the contact pad;

a first fuse on a second side of the substrate opposite the first side and coupled to the first through-via;

a second through-via in the substrate having a first end terminating on and directly contacting the contact pad; and

a second fuse on the second side of the substrate and coupled to the second through-via;

the first fuse is connected between a first connecting region and a second connecting region, and the first connecting region, the second connecting region and the first fuse are embedded in an insulating material layer on the substrate wherein a width of the first connecting region, the second connecting region and the first fuse is different from each other in a planar view; and

the second fuse is connected between a third connecting portion and a fourth connecting portion, and the third connecting portion, the fourth connecting portion and the second fuse are embedded in the insulating material layer on the substrate wherein a width of the third connecting portion, the fourth connecting portion and the second fuse is different from each other in the planar view.

2. The interposer according to claim 1, wherein the first fuse and the second fuse are disposed in a redistribution layer (RDL).

3. The interposer according to claim 1, further comprising at least one third through-via having a first end terminating on the contact pad, and at least one third fuse on the second side of the substrate, wherein each at least one third fuse is coupled to one of the at least one third through-vias.

4. The interposer according to claim 1, further comprising a first bond pad on the second side of the substrate coupled to the first fuse and a second bond pad on the second side of the substrate coupled to the second fuse.

5. The interposer according to claim 4, further comprising a first bump coupled to the first bond pad and a second bump coupled to the second bond pad.

6. The interposer according to claim 5, further comprising a third bump coupled to the contact pad.

7. The interposer according to claim 6, wherein the third bump is larger than the first bump and the second bump.

8. The interposer according to claim 6, wherein the first bump, the second bump, or the third bump comprise solder.

9. An interposer for packaging a semiconductor device, comprising:

a substrate comprising a first side and a second side opposite the first side;

a plurality of through-vias disposed in the substrate proximate the first side;

an interconnect structure disposed in the substrate proximate the second side, the interconnect structure including a plurality of fuses;

a contact pad proximate the first side, wherein at least two of the plurality of through-vias land on and directly contact the contact pad, each of the at least two of the plurality of through-vias being coupled to a respective one of the plurality of fuses;

a bump coupled to the contact pad;

a first fuse of the plurality of fuses is connected between a first connecting region and a second connecting region, and the first connecting region, the second connecting region and the first fuse are embedded in an insulating material layer in the interconnect structure wherein a width of the first connecting region, the second connecting region and the first fuse is different from each other in a planar view; and

a second fuse of the plurality of fuses is connected between a third connecting region and a fourth connecting region, and the third connecting region, the fourth connecting region and the second fuse are embedded in the insulating material layer in the interconnect structure wherein a width of the third connecting region, the fourth connecting region and the second fuse is different from each other in the planar view.

10. The interposer according to claim 9, wherein the substrate is substantially free of integrated circuit devices.

11. The interposer according to claim 9, wherein the interposer comprises a three dimensional integrated circuit (3DIC) interposer.

12. The interposer according to claim 9, wherein the plurality of fuses is programmable using a laser, before or after an integrated circuit is packaged using the interposer.

13. The interposer according to claim 9, wherein the bump comprises a first bump, further comprising an under-ball metallization (UBM) structure coupled to the interconnect structure and a plurality of second bumps coupled to the UBM structure, and wherein portions of the UBM structure are coupled to the plurality of fuses coupled to the at least two of the plurality of through-vias.

14. The interposer according to claim 13, wherein the plurality of second bumps is coupleable to an integrated circuit die.

15. The interposer according to claim 13, wherein the first bump is coupleable to a substrate, a printed circuit board (PCB), or an integrated circuit die.

16. A semiconductor device packaged using the interposer according to claim 13, wherein a plurality of contacts of an integrated circuit die is electrically coupled to the plurality of second bumps.

17. The packaged semiconductor device according to claim 16, further comprising an under-fill material disposed under the integrated circuit die.

18. The packaged semiconductor device according to claim 16, further comprising a molding compound disposed over the integrated circuit die and the interposer.

19. A method of manufacturing an interposer for packaging a semiconductor device, the method comprising:

providing a substrate;

forming a plurality of through-vias in the substrate;

forming a redistribution layer (RDL) over the substrate, the RDL including a plurality of fuses formed therein, each fuse being coupled to one of the plurality of through-vias and each fuse being formed proximate a first surface of the substrate;

forming a contact pad proximate a second surface of the substrate opposite the first surface of the substrate, the contact pad being formed and directly on at least two of the plurality of through-vias coupled to the fuses;

coupling a first bump to the contact pad;

coupling a respective second bump to each of the plurality of fuses;

a first fuse of the plurality of fuses is connected between a first connecting region and a second connecting region, and the first connecting region, the second connecting region and the first fuse are embedded in an insulating material layer in the RDL wherein a width of the first connecting region, the second connecting region and the first fuse is different from each other in a planar view; and

a second fuse of the plurality of fuses is connected between a third connecting region and a fourth connecting region, and the third connecting region, the fourth connecting region and the second fuse are embedded in the insulating material layer in the RDL wherein a width of the third connecting region, the fourth connecting region and the second fuse is different from each other in the planar view.

20. The method according to claim 19, further comprising coupling each fuse to one of the plurality of through-vias using at least one conductive line, at least one via, or a combination thereof disposed in the substrate.