Process-compatible decoupling capacitor and method for making the same

• US 8,896,096 B2
• Filed: 07/19/2012
• Issued: 11/25/2014
• Est. Priority Date: 07/19/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tu, Kuo-Chi, Chu, Wen-Ting
• Primary Examiner(s): Tran, Long K
• Application Number:
  US13/553,086
• Publication Number:
  US 20140021584A1
• Time in Patent Office: 859 Days
• Field of Search: 257/532, 365/148
• US Class Current: 257/532
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H01L 29/94 Metal-insulator-semiconductors, e.g. MOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 12/033 the capacitor extending over the transistor
• CPC Class Codes: H10B 12/09 with simultaneous manufacture of the peripheral circuit region and memory cells
• CPC Class Codes: H10B 12/50 Peripheral circuit region structures
• CPC Class Codes: H10B 63/30 comprising selection components having three or more electrodes, e.g. transistors
• CPC Class Codes: H10B 63/80 Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
• CPC Class Codes: H10N 70/063 by etching of pre-deposited switching material layers, e.g. lithography
• CPC Class Codes: H10N 70/20 Multistable switching devices, e.g. memristors
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
• CPC Class Codes: H10N 70/8833 Binary metal oxides, e.g. TaOx

Abstract

Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.

Claims

1. A device comprising:

a non-volatile memory (NVM) cell disposed within a first area, the NVM cell including a first dielectric layer; and

a decoupling capacitor disposed within a second area, wherein the decoupling capacitor comprises;

a bottom electrode;

a second dielectric layer located above, and in physical contact with, the bottom electrode, the second dielectric layer coplanar with the first dielectric layer; and

a top electrode located above, and in physical contact with, the second dielectric layer.

2. The device of claim 1, wherein the NVM cell further includes a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode-, the first dielectric layer disposed over the bottom MIM electrode, and a top MIM electrode disposed over the first dielectric layer, wherein the bottom MIM electrode includes a first metal layer, and wherein the top MIM electrode includes a second metal layer.

3. The device of claim 1, wherein each of the first and second dielectric layers include at least one of NiO, TiO, HfO, ZrO, ZnO, WO₃, Al₂O₃, TaO, MoO, and CuO.

4. The device of claim 2, wherein each of the first and second metal layers include at least one of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu.

5. The device of claim 1, wherein the decoupling capacitor comprises a structure including one of a planar-type structure, a cylinder-type structure, a bar-type structure, and a dual-damascene structure.

6. A system-on-chip (SOC) device comprising:

a resistive random-access memory (RRAM) cell, the RRAM cell including a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode, a MIM insulating layer, and a top MIM electrode, the MIM structure being situated in an inter-metal dielectric layer;

a decoupling capacitor, the decoupling capacitor comprising a bottom capacitor electrode, a capacitor insulating layer, and a top capacitor electrode, the decoupling capacitor situated in the inter-metal dielectric layer;

a logic area comprising a plurality of transistors on a substrate; and

wherein the bottom MIM electrode is coplanar with the bottom capacitor electrode, the MIM insulating layer is coplanar with the capacitor insulating layer, and the top MIM electrode is coplanar with the top capacitor electrode.

7. The SOC device of claim 6, wherein the MIM structure and the decoupling capacitor are both disposed within a single inter-metal dielectric (IMD) layer.

8. The SOC device of claim 7, further comprising a plurality of inter-metal dielectric (IMD)_layers, the decoupling capacitor and the MIM structure disposed within one layer of the plurality of inter-metal dielectric layers.

9. The SOC device of claim 7, wherein at least one logic transistor is situated below the decoupling capacitor, but is not in electrically-conducting contact with the decoupling capacitor.

10. The SOC device of claim 7, further comprising a volatile memory cell, the volatile memory cell including a capacitive memory element disposed within the single inter-metal dielectric (IMD) layer, wherein the capacitive memory element includes a bottom capacitive element electrode that is coplanar with the bottom capacitor electrode, a capacitive insulating layer that is coplanar with the capacitor insulating layer, and a top capacitive electrode that is coplanar with the top capacitor electrode.

11. The SOC device of claim 10, wherein the volatile memory cell is a dynamic random-access memory (DRAM) cell.

12. A device comprising:

a resistive random-access memory (RRAM) cell, the RRAM cell including a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode, a MIM insulating layer, and a top MIM electrode, the MIM structure being situated in an inter-metal dielectric layer; and

a decoupling capacitor including a bottom capacitor electrode disposed in a layer coplanar with the bottom MIM electrode, a capacitor insulating layer, and a top capacitor electrode disposed in the same layer as the top MIM electrode;

wherein the bottom capacitor electrode and the bottom MIM electrode include coplanar surfaces, and wherein the top capacitor electrode and the top MIM electrode include coplanar surfaces.

13. The device of claim 12, wherein the bottom capacitor electrode and the bottom MIM electrode are coupled to each other by way of a metallization stack.

14. The device of claim 12, wherein the top capacitor electrode and the top MIM electrode are coupled to each other by way of a metallization stack.

15. The device of claim 12, wherein the RRAM cell is surrounded by an inter-level dielectric.

16. The device of claim 15, wherein the decoupling capacitor is surrounded by the inter-level dielectric.

17. The device of claim 12, wherein the top capacitor electrode and the top MIM electrode include one of Pt, AlCu, TiN, Au, Ti, Ta, TaN, W, WN, and Cu.

18. The device of claim 12, wherein the capacitor insulating layer and the MIM insulating layer include the same material.