Process-compatible decoupling capacitor and method for making the same
First Claim
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1. A device comprising:
- a non-volatile memory (NVM) cell disposed within a first area, the NVM cell including a first dielectric layer; and
a decoupling capacitor disposed within a second area, wherein the decoupling capacitor comprises;
a bottom electrode;
a second dielectric layer located above, and in physical contact with, the bottom electrode, the second dielectric layer coplanar with the first dielectric layer; and
a top electrode located above, and in physical contact with, the second dielectric layer.
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Abstract
Provided is decoupling capacitor device. The decoupling capacitor device includes a first dielectric layer portion that is deposited in a deposition process that also deposits a second dielectric layer portion for a non-volatile memory cell. Both portions are patterned using a single mask. A system-on-chip (SOC) device is also provided, the SOC include an RRAM cell and a decoupling capacitor situated in a single inter-metal dielectric layer. Also a method for forming a process-compatible decoupling capacitor is provided. The method includes patterning a top electrode layer, an insulating layer, and a bottom electrode layer to form a non-volatile memory element and a decoupling capacitor.
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Citations
18 Claims
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1. A device comprising:
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a non-volatile memory (NVM) cell disposed within a first area, the NVM cell including a first dielectric layer; and a decoupling capacitor disposed within a second area, wherein the decoupling capacitor comprises; a bottom electrode; a second dielectric layer located above, and in physical contact with, the bottom electrode, the second dielectric layer coplanar with the first dielectric layer; and a top electrode located above, and in physical contact with, the second dielectric layer. - View Dependent Claims (2, 3, 4, 5)
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6. A system-on-chip (SOC) device comprising:
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a resistive random-access memory (RRAM) cell, the RRAM cell including a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode, a MIM insulating layer, and a top MIM electrode, the MIM structure being situated in an inter-metal dielectric layer; a decoupling capacitor, the decoupling capacitor comprising a bottom capacitor electrode, a capacitor insulating layer, and a top capacitor electrode, the decoupling capacitor situated in the inter-metal dielectric layer; a logic area comprising a plurality of transistors on a substrate; and wherein the bottom MIM electrode is coplanar with the bottom capacitor electrode, the MIM insulating layer is coplanar with the capacitor insulating layer, and the top MIM electrode is coplanar with the top capacitor electrode. - View Dependent Claims (7, 8, 9, 10, 11)
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12. A device comprising:
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a resistive random-access memory (RRAM) cell, the RRAM cell including a metal-insulator-metal (MIM) structure, the MIM structure comprising a bottom MIM electrode, a MIM insulating layer, and a top MIM electrode, the MIM structure being situated in an inter-metal dielectric layer; and a decoupling capacitor including a bottom capacitor electrode disposed in a layer coplanar with the bottom MIM electrode, a capacitor insulating layer, and a top capacitor electrode disposed in the same layer as the top MIM electrode; wherein the bottom capacitor electrode and the bottom MIM electrode include coplanar surfaces, and wherein the top capacitor electrode and the top MIM electrode include coplanar surfaces. - View Dependent Claims (13, 14, 15, 16, 17, 18)
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Specification