Nonplanar III-N transistors with compositionally graded semiconductor channels

• US 8,896,101 B2
• Filed: 12/21/2012
• Issued: 11/25/2014
• Est. Priority Date: 12/21/2012
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Then, Han Wui, Dasgupta, Sansaptak, Radosavljevic, Marko, Chu-Kung, Benjamin, Sung, Seung Hoon, Gardner, Sanaz K., Chau, Robert S.
• Primary Examiner(s): Fan, Michele
• Application Number:
  US13/725,546
• Publication Number:
  US 20140175515A1
• Time in Patent Office: 704 Days
• Field of Search: 257/76, 257/191, 257/327, 257/328, 257/615
• US Class Current: 257/615
• CPC Class Codes: H01L 21/02387 Group 13/15 materials
• CPC Class Codes: H01L 21/02389 Nitrides
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02458 Nitrides
• CPC Class Codes: H01L 21/0251 Graded layers
• CPC Class Codes: H01L 21/02538 Group 13/15 materials
• CPC Class Codes: H01L 21/0254 Nitrides
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0673 oriented parallel to a substrate
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/42392 fully surrounding the channel, e.g. gate-all-around
• CPC Class Codes: H01L 29/66409 Unipolar field-effect transistors
• CPC Class Codes: H01L 29/66522 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/66742 Thin film unipolar transistors
• CPC Class Codes: H01L 29/772 Field effect transistors
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78681 having a semiconductor body comprising AIIIBV or AIIBVI or AIVBVI semiconductor materials, or Se or Te
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A III-N semiconductor channel is compositionally graded between a transition layer and a III-N polarization layer. In embodiments, a gate stack is deposited over sidewalls of a fin including the graded III-N semiconductor channel allowing for formation of a transport channel in the III-N semiconductor channel adjacent to at least both sidewall surfaces in response to a gate bias voltage. In embodiments, a gate stack is deposited completely around a nanowire including a III-N semiconductor channel compositionally graded to enable formation of a transport channel in the III-N semiconductor channel adjacent to both the polarization layer and the transition layer in response to a gate bias voltage.

Claims

1. A non-planar III-N transistor disposed on a substrate, the transistor comprising:

a non-planar III-N semiconductor body comprising two wide band gap material layers on opposite {0001} sides of a III-N semiconductor channel that has a compositional grading along the c-axis between the two wide band gap III-N layers;

a gate stack comprising a gate dielectric and gate electrode, the gate stack disposed over opposing surface of the III-N semiconductor channel, said opposing surfaces span a distance between the two wide band gap material layers; and

a pair of source/drain regions embedded in or coupled to the non-planar III-N semiconductor body at opposite sides of the gate stack.

2. The III-N transistor of claim 1, wherein the III-N semiconductor channel has a band gap that decreases from at least one of the two wide band gap material layers toward a center plane orthogonal to the c-axis and centered within the III-N semiconductor channel.

3. The III-N transistor of claim 2, wherein the III-N semiconductor channel has a decreasing band gap from both of the two wide band gap material layers toward the center plane.

4. The III-N transistor of claim 3, wherein the compositional grading is uniform and symmetric about the center plane.

5. The III-N transistor of claim 2, wherein the compositional grading comprises at least one of a lower In content and higher Al content proximate to at least one of the two wide band gap material layers relative to a point distal from at least one of the two wide band gap material layers.

6. The III-N transistor of claim 5, wherein the In content varies by at least 10% between the at least one wide band gap material layer and the center plane.

7. The III-N transistor of claim 5, wherein the III-N semiconductor channel comprises InGaN and is compositionally graded from GaN proximate to each of the wide band gap material layers to approximately 10% Indium at the center plane.

8. The III-N transistor of claim 5, wherein the III-N semiconductor channel comprises InGaN and is compositionally graded from GaN proximate to a first of the wide band gap material layers to maximum In content at a second of the wide band gap material layers.

9. The III-N FET of claim 8, wherein the gate stack wraps completely around both of the two wide band gap layers to form a III-N nanowire transistor.

10. The III-N FET of claim 9, wherein the nanowire is disposed within a vertical stack of nanowires, wherein each of the nanowires has a channel region comprising a III-N semiconductor channel that is compositionally graded along the c-axis between the two wide band gap III-N layers.

11. The III-N transistor of claim 2, wherein the III-N semiconductor channel is compositionally graded with a highest Al content proximate to each of the two wide band gap material layers, decreasing toward the center plane.

12. The III-N transistor of claim 1, wherein the wide band gap material layer proximate the (000 1) surface of the non-planar III-N semiconductor body is selected from the group consisting of:

AlN, AlInN, AlGaN, or AlInGaN, and wherein the wide band gap material layer proximate the (0001) surface of the non-planar III-N semiconductor body is composed of AlN, AlInN, AlGaN, or AlInGaN.

13. A system on chip (SoC), comprising:

a power management integrated circuit (PMIC) including at least one of a switching voltage regulator or switching mode DC-DC converter; and

an RF integrated circuit (RFIC) including a power amplifier operable to operate with a cut-off frequency, F_t and maximum oscillation frequency, F_max of both at least 20 GHz, and to generate a carrier wave frequency of at least 2 GHz, wherein both of the PMIC and RFIC are monolithically integrated onto a same substrate, and wherein at least one of PMIC and RFIC include the III-N transistor of claim 1.

14. The SoC of claim 13, further comprising:

a controller of at least one of the PMIC and RFIC integrated onto the substrate, wherein the controller comprises CMOS technology fabricated with silicon field effect transistors.

15. A mobile computing device, comprising:

a touchscreen;

a battery;

an antenna;

a DC-to-DC converter coupled to the battery; and

a wireless transmitter further including a power amplifier (PA), wherein at least one of the DC-to-DC converter and the PA comprises the III-N transistor as in claim 1.

16. The mobile computing device of claim 15 where the DC-to-DC converter comprises a first III-N transistor as in claim 1, and the PA employs a second III-N transistor as in claim 1.

17. A non-planar III-N transistor disposed on a substrate, the transistor comprising:

a non-planar III-N semiconductor body comprising two wide band gap crystalline material layers on opposite sides of a III-N semiconductor channel that has a compositional grading along the c-axis between the two wide band gap crystalline material layers;

a gate stack comprising a gate dielectric and gate electrode, the gate stack disposed over opposing surface of the III-N semiconductor channel, said opposing surfaces span a distance between the two wide band gap crystalline material layers; and

a pair of source/drain regions embedded in or coupled to the non-planar III-N semiconductor body at opposite sides of the gate stack;

wherein a transport channel is formed in the III-N semiconductor channel adjacent to both opposing surfaces in response to a bias voltage on a gate electrode exceeding a threshold voltage of the non-planar III-N transistor.

18. The III-N transistor of claim 17, wherein the transport channel adjacent to a first of the wide band gap crystalline material layers proximate to a (0001) surface of the III-N semiconductor channel forms a continuous transport channel spanning the (0001) surface and a plurality of {1010} surfaces of the III-N semiconductor channel.

19. The III-N transistor of claim 17, wherein the III-N semiconductor channel has a decreasing band gap from both of the two wide band gap crystalline material layers toward a plane through the center of III-N semiconductor channel.