Via structure and via etching process of forming the same
First Claim
Patent Images
1. An integrated circuit structure, comprising:
- a semiconductor substrate;
a hard mask layer formed on the semiconductor substrate;
at least a conductive layer formed in the hard mask layer; and
a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.
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Abstract
An integrated circuit structure includes a semiconductor substrate and a hard mask layer formed on the semiconductor substrate. The integrated circuit structure further includes at least a conductive layer formed in the hard mask layer and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall.
56 Citations
20 Claims
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1. An integrated circuit structure, comprising:
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a semiconductor substrate; a hard mask layer formed on the semiconductor substrate; at least a conductive layer formed in the hard mask layer; and a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. An integrated circuit structure, comprising:
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a semiconductor substrate; a hard mask layer formed on the semiconductor substrate; a via extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the via has a round corner and a tapered sidewall; a conductive material disposed in the via; and an insulating material between sidewalls of the conductive material and sidewalls of the via. - View Dependent Claims (12, 13, 14, 15, 16)
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17. An integrated circuit structure, comprising:
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a semiconductor substrate; a hard mask layer formed on the semiconductor substrate; a conductive contact extending from the hard mask layer to at least a portion of the semiconductor substrate, wherein the conductive contact has a round corner and a tapered sidewall; and an insulating material between sidewalls of the conductive contact and the semiconductor substrate. - View Dependent Claims (18, 19, 20)
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Specification