Common electrode driving method, common electrode driving circuit and liquid crystal display

• US 8,896,583 B2
• Filed: 04/18/2011
• Issued: 11/25/2014
• Est. Priority Date: 04/16/2010
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: Xue, Hailin, Xu, Yubo, Li, Cheng, Zhan, Hongming, Zhang, Jidong
• Primary Examiner(s): Kumar, Srilakshmi K
• Assistant Examiner(s): NOKHAM, JAMES S
• Application Number:
  US13/376,495
• Publication Number:
  US 20120092312A1
• Time in Patent Office: 1,317 Days
• Field of Search: 345 87-100, 345/208
• US Class Current: 345/205
• CPC Class Codes: G09G 2320/0219 Reducing feedthrough effects in active matrix panels, i.e. voltage changes on the scan electrode influencing the pixel voltage due to capacitive coupling
• CPC Class Codes: G09G 3/3655 Details of drivers for counter electrodes, e.g. common electrodes for pixel capacitors or supplementary storage capacitors
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A common electrode driving method, comprises: generating a first common electrode signal to be applied to a storage electrode line of each row of pixels on an array substrate, and a second common electrode signal to be applied to a common electrode forming a liquid crystal capacitance with pixel electrodes of each row of pixels on the array substrate, the first common electrode signal being opposite to a gate signal for gate electrodes applied to the corresponding row of pixels in terms of transition timing; and inputting the first common electrode signal to each row of pixels, and inputting the second common electrode signal to the common electrode.

Claims

1. A common electrode driving method, comprising:

inputting the first common electrode signal to each row of pixels, and inputting the second common electrode signal to the common electrode,

wherein the first common electrode signal and the gate signal applied to the corresponding row of pixels are transited synchronously and a polarity of a difference between a level of the first common electrode signal after the transition and a level of the first common electrode signal before transition is opposite to a polarity of a difference between a level of the gate signal applied to the corresponding row of pixels after the transition and a level of the gate signal applied to the corresponding row of pixels before transition,

wherein the first common electrode signal and the second common electrode signal are generated by a driving signal generation circuit, and the driving signal generation circuit comprises;

a first driving signal generation unit for generating the second common electrode signal; and

a second driving signal generation unit for generating the first common electrode signal by generating a transition timing signal and superposing the transition timing signal on the second common electrode signal generated by the first driving signal generation unit.

2. The common electrode driving method according to claim 1, wherein an absolute value of a charge change amount due to the transition of the first common electrode signal in a storage capacitance is equal to that of a charge change amount due to the transition of the gate signal in a parasitic capacitance connected in series with a storage capacitance, and change directions of them are opposite to each other.

3. The common electrode driving method according to claim 2, wherein the storage capacitance has a structure in which the pixel electrode is overlapped with the storage electrode line, and a difference between a high level and a low level of the first common electrode signal is equal to [Cgd*(Vgh−

Vgl)]/Cst, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst is a capacity value of the storage capacitance, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

4. The common electrode driving method according to claim 2, wherein the storage capacitance has a structure in which the pixel electrode is respectively overlapped with the storage electrode line and the gate line, and a difference between a high level and a low level of the first common electrode signal is equal to [Cgd*(Vgh−

Vgl)]/Cst1, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst1 is a capacity value of a part of the storage capacitance on the storage electrode line, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

5. The common electrode driving method according to claim 1, wherein the common electrode is formed on a color-filter substrate or the array substrate.

6. A common electrode driving circuit, comprising:

a common electrode signal output terminal for inputting the first common electrode signal to each row of pixels, and inputting the second common electrode signal to the common electrode,

wherein the first common electrode signal and the gate signal applied to the corresponding row of pixels are transited synchronously and a polarity of a difference between a level of the first common electrode signal after the transition and a level of the first common electrode signal before transition is opposite to a polarity of a difference between a level of the gate signal applied to the corresponding row of pixels after the transition and a level of the gate signal applied to the corresponding row of pixels before transition,

wherein the driving signal generation circuit comprises;

a first driving signal generation unit for generating the second common electrode signal; and

a second driving signal generation unit for generating the first common electrode signal by generating a transition timing signal and superposing the transition timing signal on the second common electrode signal generated by the first driving signal generation unit.

7. The common electrode driving circuit according to claim 6, wherein an absolute value of a charge change amount due to the transition of the first common electrode signal in a storage capacitance is equal to that of a charge change amount due to the transition of the gate signal in a parasitic capacitance connected in series with a storage capacitance, and change directions of them are opposite to each other.

8. The common electrode driving circuit according to claim 7, wherein the storage capacitance has a structure in which the pixel electrode is overlapped with the storage electrode line, and a difference between a high level and a low level of the first common electrode signal generated by the driving signal generation circuit is equal to [Cgd*(Vgh−

Vgl)]/Cst, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst is a capacity value of the storage capacitance, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

9. The common electrode driving circuit according to claim 7, wherein the storage capacitance has a structure in which the pixel electrode is respectively overlapped with the storage electrode line and the gate line, and a difference between a high level and a low level of the first common electrode signal generated by the driving signal generation circuit is equal to [Cgd*(Vgh−

Vgl)]/Cst1, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst1 is a capacity value of a part of the storage capacitance on the storage electrode line, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

10. A liquid crystal display, comprising:

a liquid crystal panel; and

a driver for driving the liquid crystal panel,

wherein the liquid crystal panel is formed by assembling an array substrate and a color-filter substrate with a liquid crystal layer filled therebetween, the driver comprising a gate driver, a data driver and a common electrode driver,

wherein the common electrode driver is used for generating a first common electrode signal to be applied to a storage electrode line of each row of pixels on the array substrate, and a second common electrode signal to be applied to a common electrode forming a liquid crystal capacitance with pixel electrodes of each row of pixels on the array substrate, and inputting the generated first common electrode signal to each row of pixels and inputting the generated second common electrode signal to the common electrode, and

wherein the first common electrode signal is opposite to a gate signal applied to gate electrodes in the corresponding row of pixels in terms of transition timing,

wherein the first common electrode signal and the gate signal applied to the corresponding row of pixels are transited synchronously and a polarity of a difference between a level of the first common electrode signal after the transition and a level of the first common electrode signal before transition is opposite to a polarity of a difference between a level of the gate signal applied to the corresponding row of pixels after the transition and a level of the gate signal applied to the corresponding row of pixels before transition,

wherein the common electrode driver, comprises;

a first driving signal generation unit for generating the second common electrode signal; and

a second driving signal generation unit for generating the first common electrode signal by generating a transition timing signal and superposing the transition timing signal on the second common electrode signal generated by the first driving signal generation unit.

11. The liquid crystal display according to claim 10, wherein an absolute value of a charge change amount due to the transition of the first common electrode signal in a storage capacitance is equal to that of a charge change amount due to the transition of the gate signal in the parasitic capacitance connected in series with the storage capacitance, and change directions of them are opposite to each other.

12. The liquid crystal display according to claim 11, wherein the storage capacitance has a structure in which the pixel electrode is overlapped with the storage electrode line, and a difference between a high level and a low level of the first common electrode signal is equal to [Cgd*(Vgh−

Vgl)]/Cst, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst is a capacity value of the storage capacitance, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

13. The liquid crystal display according to claim 11, wherein the storage capacitance has a structure in which the pixel electrode is respectively overlapped with the storage electrode line and the gate line, and a difference between a high level and a low level of the first common electrode signal is equal to [Cgd*(Vgh−

Vgl)]/Cst1, where Cgd is a capacity value of the parasitic capacitance connected in series with the storage capacitance, Cst1 is a capacity value of a part of the storage capacitance on the storage electrode line, and Vgh and Vgl are an ON voltage and an OFF voltage of a gate electrode, respectively.

14. The liquid crystal display according to claim 10, wherein the common electrode is formed on the color-filter substrate or the array substrate.