Video signal processing circuit, video signal processing method, display device, and electronic apparatus

• US 8,896,758 B2
• Filed: 04/30/2012
• Issued: 11/25/2014
• Est. Priority Date: 06/14/2011
• Status: Expired due to Fees

• Current Assignee: JOLED Inc.
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Funatsu, Yohei
• Primary Examiner(s): YENKE, BRIAN P
• Application Number:
  US13/460,177
• Publication Number:
  US 20120320274A1
• Time in Patent Office: 939 Days
• Field of Search: 348/687, 348/730, 345/690
• US Class Current: 348/687
• CPC Class Codes: G09G 2320/0626 for control of overall brightness
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 2360/16 Calculation or use of calculated indices related to luminance levels in display data
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters

Abstract

A video signal processing circuit includes: a control unit that calculates a luminance integrated value on the basis of an input video signal and performs luminance control for the video signal on the basis of the calculated luminance integrated value, wherein the control unit calculates the luminance integrated value at a period shorter than time equivalent to one frame.

Claims

1. A video signal processing circuit comprising:

a first control system that is configured to calculate a first luminance integrated value periodically at a period equal to a first unit of time equivalent to one frame and controls a video signal on the basis of the calculated first luminance integrated value; and

a second control system that is provided at a post-stage of the first control system and that is configured to calculate a second luminance integrated value periodically at a period equal to a second unit of time that is shorter than the first unit of time and controls the video signal on the basis of the calculated second luminance integrated value,

wherein the first luminance integrated value is calculated for each frame and the video signal for a current frame is controlled on the basis of the calculated first luminance integrated value of a preceding frame,

the second control system is configured to calculate an average luminance value on the basis of the controlled video signal output from the first control system for each time period equivalent to the second unit of time, and

the second control system is configured to calculate the second luminance integrated value by integrating each respective average luminance value that has been calculated from a timing corresponding to a beginning of the current frame to a most recent timing and controls the video signal on the basis of a most recent second luminance integrated value.

2. The video signal processing circuit according to claim 1, wherein:

the first control system is configured to control the video signal by multiplying the video signal by a first value, the first value being updated each frame based on the most recently calculated first luminance integrated value, and

the second control system is configured to control the video signal by multiplying an output signal of the first control system by a second value, the second value being updated each second unit of time based on the most recently calculated second luminance integrated value.

3. The video signal processing circuit according to claim 1,

wherein the first control system reduces the amplitude of the video signal when the first luminance integrated value is larger than a control target value, and

the second control system reduces the amplitude of the video signal when the second luminance integrated value is larger than the control target value.

4. The video signal processing circuit according to claim 1, wherein the second unit of time is equivalent to an integer number of lines.

5. The video signal processing circuit according to claim 4, wherein the second unit of time is equivalent to one line.

6. The video signal processing circuit according to claim 4, wherein the second unit of time is equivalent to plural lines.

7. The video signal processing circuit according to claim 1, wherein the second unit of time is equivalent to one dot.

8. A display device comprising the video signal processing circuit of claim 1.

9. The display device according to claim 8, wherein:

the first control system is configured to control the video signal by multiplying the video signal by a first value, the first value being updated each frame based on the most recently calculated first luminance integrated value, and

the second control system is configured to control the video signal by multiplying an output signal of the first control system by a second value, the second value being updated each second unit of time based on the most recently calculated second luminance integrated value.

10. The display device according to claim 8,

wherein the first control system reduces the amplitude of the video signal when the first luminance integrated value is larger than a control target value, and

the second control system reduces the amplitude of the video signal when the second luminance integrated value is larger than the control target value.

11. The display device according to claim 8, wherein the second unit of time is equivalent to an integer number of lines.

12. The display device according to claim 11, wherein the second unit of time is equivalent to one line.

13. The display device according to claim 11, wherein the second unit of time is equivalent to plural lines.

14. The display device according to claim 8, wherein the second unit of time is equivalent to one dot.

15. An electronic apparatus comprising the display device of claim 8.

16. The electronic apparatus according to claim 15, wherein:

the first control system is configured to control the video signal by multiplying the video signal by a first value, the first value being updated each frame based on the most recently calculated first luminance integrated value, and

the second control system is configured to control the video signal by multiplying an output signal of the first control system by a second value, the second value being updated each second unit of time based on the most recently calculated second luminance integrated value.

17. The electronic apparatus according to claim 15,

wherein the first control system reduces the amplitude of the video signal when the first luminance integrated value is larger than a control target value, and

the second control system reduces the amplitude of the video signal when the second luminance integrated value is larger than the control target value.

18. The electronic apparatus according to claim 15, wherein the second unit of time is equivalent to an integer number of lines.

19. The electronic apparatus according to claim 18, wherein the second unit of time is equivalent to one line.

20. The electronic apparatus according to claim 18, wherein the second unit of time is equivalent to plural lines.

21. The electronic apparatus according to claim 15 wherein the second unit of time is equivalent to one dot.