Pillar-shaped nonvolatile memory and method of fabrication

• US 8,897,056 B2
• Filed: 07/29/2013
• Issued: 11/25/2014
• Est. Priority Date: 11/16/1998
• Status: Expired due to Fees

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Johnson, Mark G., Lee, Thomas H., Subramanian, Vivek, Farmwald, Paul Michael, Cleeves, James M.
• Primary Examiner(s): LE, THONG QUOC
• Application Number:
  US13/952,990
• Publication Number:
  US 20130314970A1
• Time in Patent Office: 484 Days
• Field of Search: 365/115, 365/100, 365/175, 365/105
• US Class Current: 365/115
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 17/06 using diode elements G11C17/14 takes precedence
• CPC Class Codes: G11C 17/14 in which contents are determined by selectively establishing, breaking or modifying connecting links by permanently altering the state of coupling elements, e.g. PROM
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: G11C 17/165 Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses digital stores using resistance random access memory elements G11C13/0002
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/76 Array using an access device for each cell which being not a transistor and not a diode
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H10B 63/84 arranged in a direction perpendicular to the substrate, e.g. 3D cell arrays
• CPC Class Codes: H10N 70/011 Manufacture or treatment of multistable switching devices
• CPC Class Codes: H10N 70/826 adapted for essentially vertical current flow, e.g. sandwich or pillar type devices

Abstract

A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Claims

1. A pillar-shaped memory cell comprising:

an input terminal and an output terminal;

a steering element; and

a non-volatile state change element coupled in series with the steering element,

wherein the steering element and state change element comprise a pillar coupled between the input terminal and the output terminal.

2. The pillar-shaped memory cell of claim 1, wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.

3. The pillar-shaped memory cell of claim 1, wherein the state change element comprises a reversible resistance-switching element.

4. The pillar-shaped memory cell of claim 1, wherein the state change element is capable of having more than two resistance states.

5. The pillar-shaped memory cell of claim 1, wherein the state change element is rewriteable.

6. The pillar-shaped memory cell of claim 1, wherein the state change element comprises a multi-state antifuse.

7. A three-dimensional memory array including:

a first memory level comprising a first plurality of the pillar-shaped memory cells of claim 1; and

a second memory level disposed vertically above the first memory level, the second memory level comprising a second plurality of the pillar-shaped memory cells of claim 1.

8. A method of forming a pillar-shaped memory cell, the method comprising:

forming a steering element; and

forming a non-volatile state change element in series with the steering element,

wherein the steering element and state change element comprise a pillar coupled between an input terminal and an output terminal of the memory cell.

9. The method of claim 8, wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.

10. The method of claim 8, wherein the state change element comprises a reversible resistance-switching element.

11. The method of claim 8, wherein the state change element is capable of having more than two resistance states.

12. The method of claim 8, wherein the state change element is rewriteable.

13. The method of claim 8, wherein the state change element comprises a multi-state antifuse.

14. A method of forming a three-dimensional memory array, the method comprising:

forming a first memory level comprising a first plurality of the pillar-shaped memory cells formed according to the method of claim 8; and

forming a second memory level vertically above the first memory level, the second memory level comprising a second plurality of the pillar-shaped memory cells formed according to the method of claim 8.

15. A memory cell comprising:

a steering element; and

a non-volatile state change element coupled in series with the steering element,

wherein the steering element and the state change element are vertically stacked.

16. The memory cell of claim 15, wherein the steering element comprises a p-n diode, a p-i-n diode or a Schottky diode.

17. The memory cell of claim 15, wherein the state change element comprises a reversible resistance-switching element.

18. The memory cell of claim 15, wherein the state change element is capable of having more than two resistance states.

19. The memory cell of claim 15, wherein the state change element is rewriteable.

20. The memory cell of claim 15, wherein the state change element comprises a multi-state antifuse.

21. A three-dimensional memory array including:

a first memory level comprising a first plurality of the memory cells of claim 15; and

a second memory level disposed vertically above the first memory level, the second memory level comprising a second plurality of the memory cells of claim 15.