Nonvolatile memory apparatus and method for driving the same

• US 8,897,058 B2
• Filed: 12/19/2012
• Issued: 11/25/2014
• Est. Priority Date: 08/30/2012
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ahn, Chang Yong
• Primary Examiner(s): HIDALGO, FERNANDO N
• Application Number:
  US13/720,764
• Publication Number:
  US 20140063896A1
• Time in Patent Office: 706 Days
• Field of Search: 365/145, 365/148, 365/158, 365/163, 365/189.16
• US Class Current: 365/145
• CPC Class Codes: G11C 11/02 using magnetic elements
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 13/0002 using resistive RAM [RRAM] elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0064 Verifying circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods

Abstract

A method for driving a nonvolatile memory apparatus includes: a data storage preparation step of setting a write control voltage to a first level of voltage; a data storage step of driving a driving transistor through the write control voltage to generate a write current, and storing an external data in a memory cell through the write current; a data detection step of varying the write control voltage by a predetermined level from a preset voltage level, and reading the data stored in the memory cell; and a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of the determining.

Claims

1. A method for driving a nonvolatile memory apparatus which comprises a control unit and a write driver, comprising:

a data storage preparation step of setting a write control voltage generated by the control unit to a first level of voltage;

a data storage step of driving a driving transistor included in the write driver in response to the write control voltage to generate a write current, and storing an external data in a memory cell through the use of the write current;

a data detection step of changing the write control voltage by a predetermined level from a preset voltage level, when reading the data stored in the memory cell; and

a data verification step of determining whether the stored data coincides with the external data or not, and repeating the data storage step and the data detection step according to a result of whether the stored data coincides with the external data or not,

wherein a level of the write control voltage is changed by the control unit.

2. The method according to claim 1, wherein, in the data detection step,

when the voltage level of the write control voltage is increased by a determined level, the write current is increased at the data storage step.

3. The method according to claim 1, wherein, in the data detection step,

when the voltage level of the write control voltage is decreased by a predetermined level, the write current is increased at the data storage step.

4. The method according to claim 1, wherein, in the data detection step comprises,

disconnecting the driving transistor and the memory cell.

5. The method according to claim 1, wherein, in the data verification step,

when the stored data does not coincide with the external data, the data storage step, data detection step, and data verification step are all performed again.

6. The method according to claim 1, wherein when the stored data coincides with the external data, the operation of the data verification step is ended.

7. The method according to claim 1, wherein the memory cell comprises a resistive memory cell.

8. The method according to claim 1, wherein the nonvolatile memory apparatus comprises a phase change random access memory.

9. The method according to claim 1, wherein the nonvolatile memory apparatus comprises a ferroelectric random access memory.

10. The method according to claim 1, wherein the nonvolatile memory apparatus comprises a magnetic random access memory.

11. A method for driving a nonvolatile memory apparatus including a control unit and a write driver, which repeats a write operation and a verification read operation during a data input operation, until external data and stored data coincide with each other,

wherein the write operation comprises the steps of:

driving a driving transistor included in the write driver in response to a write control voltage generated by the control unit to generate a write current; and

storing the external data in a memory cell through the use of the write current, and

the verification read operation comprises the step of changing the write control voltage by a predetermined level from a preset voltage level, when detecting the data stored in the memory cell, in order for next write operation,

wherein a level of the write control voltage is changed by the control unit.

12. The method according to claim 11, wherein when the voltage level of the write control voltage is increased by a predetermined level during the verification read operation, the write current increased during the write operation.

13. The method according to claim 11, wherein when the voltage level of the write control voltage is decreased by a predetermined level during the verification read operation, the write current is increased during the write operation.

14. The method according to claim 11, wherein while the level of the write control voltage is changed during the verification read operation, the driving transistor and the memory cell are disconnected.

15. The method according to claim 11, wherein the write operation and the verification read operation are repeated until the stored data coincides with the external data.

16. The method according to claim 11, wherein the memory cell comprises a resistive memory cell.

17. The method according to claim 11, wherein the nonvolatile memory apparatus comprises a phase change random access memory.

18. The method according to claim 11, wherein the nonvolatile memory apparatus comprises a ferroelectric random access memory.

19. The method according to claim 11, wherein the nonvolatile memory apparatus comprises a magnetic random access memory.