Nonvolatile memory devices

• US 8,897,089 B2
• Filed: 12/12/2011
• Issued: 11/25/2014
• Est. Priority Date: 12/30/2010
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, JinTae, Kim, Doogon
• Primary Examiner(s): BERNSTEIN, ALLISON
• Application Number:
  US13/323,275
• Publication Number:
  US 20120170369A1
• Time in Patent Office: 1,079 Days
• Field of Search: 365/185.05, 365/207, 365/230.06, 365/230.08, 257314-316, 257/324, 257/E27.103, 257/E29.3, 257/E29.309
• US Class Current: 365/207
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistors
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/20 characterised by three-dimensional arrangements, e.g. with cells on different height levels
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

Nonvolatile memory devices including memory cell arrays with first bit line regions and common source tapping regions which are alternately disposed on a substrate along a direction, a page buffer including second bit line regions aligned with the first bit line regions and page buffer tapping regions aligned with the common source tapping regions, and a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.

Claims

1. A nonvolatile memory device, comprising:

a memory cell array including a plurality of first bit line regions alternating with a plurality of common source tapping regions on a substrate;

a page buffer including a plurality of second bit line regions aligned with the first bit line regions and a plurality of page buffer tapping regions aligned with the common source tapping regions; and

a plurality of bit lines spaced apart from one another and extending to the second bit line regions from the first bit line regions.

2. The nonvolatile memory device of claim 1, wherein

each of the page buffer tapping regions includes at least one page buffer tapping line,

the page buffer tapping line is in parallel with the plurality of bit lines, and

the page buffer tapping line is configured to supply power to the page buffer.

3. The nonvolatile memory device of claim 2, wherein

the page buffer further includes a plurality of conductive lines spaced apart from one another and extending in a direction perpendicular to the plurality of bit lines, and

the conductive lines are connected with the page buffer tapping lines via a plurality of contact plugs.

4. The nonvolatile memory device of claim 2, wherein each of the page buffer tapping regions includes a plurality of page buffer tapping lines, at least one of the page buffer tapping lines configured to supply a power supply voltage and at least one of the page buffer tapping lines configured to supply a ground voltage.

5. The nonvolatile memory device of claim 2, wherein

each of the page buffer tapping regions includes a plurality of page buffer tapping lines, and

each of the page buffer tapping regions includes a dummy bit line between at least one adjacent pair of the page buffer tapping lines.

6. The nonvolatile memory device of claim 2, wherein

each of the page buffer tapping regions includes only one page buffer tapping line, and

the nonvolatile memory device is configured to alternately supply a power supply voltage and a ground voltage through the only one page buffer tapping line along a direction perpendicular to the plurality of bit lines.

7. The nonvolatile memory device of claim 1, wherein a width of each of the page buffer tapping regions is one of less than and identical to a width of each of the common source tapping regions.

8. The nonvolatile memory device of claim 1, wherein a width of each of the page buffer tapping regions is 10 times a width of each of the plurality of bit lines.

9. The nonvolatile memory device of claim 1, wherein a width of each of the page buffer tapping regions is 8 times a width of each of the plurality of bit lines.

10. The nonvolatile memory device of claim 1, wherein

the memory cell array further includes a plurality of cell strings in each of the first bit line regions, and

each of the plurality of cell strings includes a plurality of cell transistors stacked in a direction perpendicular to the substrate.

11. The nonvolatile memory device of claim 10, wherein each of the common source tapping regions includes at least one common source tapping line configured to supply power to a common source line of the plurality of cell strings.

12. The nonvolatile memory device of claim 11, wherein each of the common source tapping regions includes a plurality of common source tapping lines, at least one of the common source tapping lines configured to supply a power supply voltage and at least one of the common source tapping lines configured to supply a ground voltage.

13. The nonvolatile memory device of claim 11, wherein

each of the common source tapping regions includes a plurality of common source tapping lines, and

each of the common source tapping regions includes a dummy bit line between at least one adjacent pair of common source tapping lines.

14. The nonvolatile memory device of claim 11, wherein

each of the common source tapping regions includes only one common source tapping line, and

the nonvolatile memory device is configured to alternately supply a power supply voltage and a ground voltage through the only one common source tapping line along a direction perpendicular to the plurality of bit lines.

15. The nonvolatile memory device of claim 11, wherein the common source line includes a plurality of common source regions spaced apart from one another and extending in a direction perpendicular to the plurality of bit lines.

16. A nonvolatile memory device, comprising:

bit line groups alternating with tapping line groups, each of the bit line groups including a plurality of memory cell strings and a plurality of bit lines connected to a page buffer, each of the tapping line groups including

at least one common source tapping line configured to supply power to a common source line connected to the plurality of memory cell strings, and

at least one page buffer tapping line configured to supply power to the page buffer.

17. A nonvolatile memory device, comprising:

a first mesh structure including a plurality of common source regions of a common source line extending in a first direction and a plurality of common source tapping lines extending in a second direction, the common source tapping lines connected to the common source regions at cross points.

18. The nonvolatile memory device of claim 17, further comprising:

a second mesh structure including a plurality of page buffer tapping lines extending in the second direction and a plurality of conductive lines extending in the first direction, the page buffer tapping lines connected to the conductive lines.

19. The nonvolatile memory device of claim 18, wherein

the first mesh structure is part of a vertical channel memory array and configured to distribute power across the common source line,

the second mesh structure is part of a page buffer and configured to distribute power across the page buffer, and

the common source tapping lines and the page buffer tapping lines are in a same interconnect level with, and parallel to, a plurality of bit lines.

20. The nonvolatile memory device of claim 18, wherein

the first mesh structure is configured to supply an about stable voltage to the common source line, and

the second mesh structure is configured to supply an about stable voltage to an active region of the page buffer.