Communication among partitioned devices

• US 8,898,246 B2
• Filed: 07/29/2004
• Issued: 11/25/2014
• Est. Priority Date: 07/29/2004
• Status: Active Grant

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Inventors: Gostin, Gary Belgrave, McMahan, Larry N., Schroeder, Michael A., Warner, Craig W., Adkisson, Richard W., Chong, Huai-Ter Victor, Binford, David M., Shaw, Mark Edward, Fevrier, Thierry, Cowan, Joe P., Rostampour, Arad
• Primary Examiner(s): Najjar, Saleh
• Assistant Examiner(s): Shepperd, Eric W
• Application Number:
  US10/902,341
• Publication Number:
  US 20060026299A1
• Time in Patent Office: 3,771 Days
• Field of Search: 709213-216, 709/208, 709/212, 719/312, 710/260, 710/262, 710/317, 710/100, 710/107, 726/27, 726/29
• US Class Current: 709/213
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes

Abstract

A computing device having partitions, and a method of communicating between partitions, are disclosed wherein at least one partition comprises: at least one register substantially always accessible to other partitions and capable of defining an address area; at least one address area that may be accessible to other partitions and is capable of being defined by the at least one register; and address areas other than the at least one accessible address area that are not accessible to other partitions. A method of processing interrupts comprising receiving an interrupt, assessing the origin of the interrupt, accepting, rejecting, or further assessing the interrupt, depending on its origin, when further assessing the interrupt, accepting or rejecting the interrupt depending on its contents, and forwarding accepted interrupts but not rejected interrupts to a target processor, and a device carrying out that method are also disclosed.

Claims

1. A computing device having partitions, wherein at least one partition comprises:

at least one cell;

at least one register that in normal use of the device is accessible to other partitions and capable of defining an accessible address area; and

the at least one partition is arranged to permit other partitions to access at least one accessible address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area;

wherein the at least one partition comprises information associated with the at least one register and specifying which other partitions are permitted to access the accessible address area identified by the at least one register; and

wherein the at least one register comprises a sharing set register within the at least one partition containing the information specifying which other partitions are permitted to access the accessible address area.

2. A computing device according to claim 1, wherein the at least one accessible address area is readable, but not writable, from another partition.

3. A computing device according to claim 1, wherein the at least one partition is arranged to identify from which partition an attempt to access the at least one accessible address area originates, and to permit access from only some other partitions.

4. A computing device according to claim 3, wherein each partition comprises at least one cell, the device further comprises a communications system for communication between cells, and wherein at least some cells are arranged to discriminate between communications from cells in the same partition having said communications medium in common, cells in a partition permitted to address the at least one accessible address area, and cells in a partition not permitted to address the at least one accessible address area.

5. A computing device according to claim 1, wherein the at least one register comprises one or more pairs of registers, each pair of registers in use specifying the upper and lower bounds of a memory area accessible to at least one other partition.

6. A computing device according to claim 1, wherein at least a second partition comprises:

at least one register always accessible to other partitions and capable of defining an accessible address area; and

a memory controller arranged to permit other partitions to access at least one accessible address area defined by the at least one register and to deny other partitions access to address areas other than the at least one accessible address area.

7. A computing device according to claim 1, wherein each partition includes at least one central processing unit.

8. A computing device according to claim 1, wherein the sharing set register within the at least one partition comprises, for each other partition that may be permitted to access the accessible address area, information indicating whether that other partition is permitted to access the accessible address area.

9. A computing device according to claim 1, wherein the at least one register comprises registers identifying a plurality of memory areas, and the at least one partition comprises information associated with the registers and specifying which other partitions are permitted to access each of the accessible address areas identified by the registers.

10. A computing device according to claim 9, wherein each of the accessible address areas is assigned to one or more other partitions, and only the assigned partitions are permitted to access that accessible address area.

11. A computing device according to claim 10, wherein each partition comprises at least one cell, each cell comprising a central processing unit, each of the accessible address areas is assigned to one or more specific cells in one or more other partitions, and only the assigned cells are permitted to access that accessible address area.

12. A computing device according to claim 1, wherein the partitions are arranged to communicate by sending interrupt signals, and the at least one partition is provided with information specifying from which other partitions it will accept interrupt signals.

13. A computing device according to claim 12, wherein the at least one partition is provided with information specifying what interrupt signals it will accept from other partitions.

14. A computing device according to claim 13, wherein the at least one partition is provided with information specifying, for each other partition, what interrupt signals the at least one partition will accept from that other partition.

15. A computing device according to claim 1, wherein the partitions are arranged to communicate by sending interrupt signals, and the at least one partition is arranged, if it receives an unacceptable interrupt signal, to discard that signal and to generate a signal indicating that an unacceptable interrupt signal has been received.

16. A computing device according to claim 15, wherein an interrupt signal includes an interrupt target and an interrupt vector, and where interrupt validation consists of:

if the interrupt is from a disallowed source, the interrupt is discarded;

if the interrupt is from a trusted source, the interrupt is forwarded to the interrupt target;

if the interrupt is from a non-trusted source and the interrupt target is disallowed, the interrupt is discarded;

if the interrupt is from a non-trusted source, the interrupt target is allowed, but the interrupt vector is disallowed, then the interrupt is discarded and replaced by an interrupt to the specified interrupt target, where the interrupt vector is specified error interrupt vector.

17. A method of communicating between partitions, comprising:

providing in a partition at least one register accessible to other partitions and defining an accessible address area, wherein the at least one register in the partition comprises a register specifying which other partitions are permitted to access the accessible memory area to which that register refers;

permitting at least one other partition to access at least one accessible address area defined by the at least one register; and

preventing other partitions from accessing address areas other than the at least one accessible address area.

18. A method according to claim 17, comprising permitting a partition to read from, but not to write to, at least one accessible memory area in another partition.

19. A method according to claim 17, comprising permitting other partitions to access only the at least one register and the accessible address areas defined by the at least one register.

20. A method according to claim 17, wherein the at least one register comprises one or more pairs of registers, each pair of registers specifying the upper and lower bounds of an accessible memory area accessible to other partitions.

21. A method according to claim 17, comprising permitting each of at least two partitions to access a defined accessible address area in the other of the at least two partitions.

22. A method according to claim 21, comprising providing a group of partitions, and in each partition of the group of partitions that is to communicate with other partitions in the group of partitions, an accessible address area that is accessible only to the other partitions of the group of partitions.

23. A method according to claim 17, wherein the register specifying which other partitions are permitted to access the accessible memory area to which that register refers comprises information specifying, for each of a plurality of other partitions, whether each of those partitions is permitted to access the accessible memory area to which that register refers.

24. A method according to claim 17, comprising:

sending a memory access request to a first partition from a second partition;

when the second partition does not receive a response from the first partition to the request within a time limit, fabricating data for use within the second partition indicating that a valid response is not available.

25. A method according to claim 24, comprising:

when an unusable response is received, discarding the response and fabricating the data for use within the second partition indicating that a valid response is not available.

26. A method according to claim 25, comprising:

when an unusable response is discarded, taking no action until the time limit, and when no usable response has been received within the time limit fabricating the data for use within the second partition indicating that a valid response is not available.

27. A method according to claim 24, comprising:

when the second partition has not received a response from the first partition within the time limit, and when the second partition subsequently desires other information from the first partition,

fabricating the data for use within the second partition indicating that a valid response is not available without submitting a request for the other information to the first partition.

28. A computing device having partitions, wherein at least one partition comprises:

at least one first means accessible to other partitions and capable of defining an accessible address area; and

second means within the partition for permitting other partitions access to at least one accessible address area defined by the at least one first means and preventing other partitions from accessing other address areas.

29. A computing device according to claim 28, further comprising an interface device for communication between first and second partitions, the interface device comprising:

first means for sending a memory access request to a first partition from a second partition with which the interface device is associated;

second means for fabricating data for use within the second partition indicating that a valid response is not available when the interface device does not receive a response from the first partition to the request within a time limit.

30. A computing device according to claim 29, wherein the interface device further comprises:

means for discarding a response received from the first partition when the response received is unusable, and fabricating the data for use within the second partition indicating that a valid response is not available.

31. A computing device according to claim 29, wherein the interface device is arranged, when an unusable response is discarded, to take no action until the time limit, and when no usable response has been received within the time limit fabricating the data for use within the second partition indicating that a valid response is not available.

32. A computing device according to claim 29, wherein the interface device is arranged, when the second partition has not received a response from the first partition within the time limit, and when the second partition subsequently desires other information from the first partition, to fabricate the data for use within the second partition indicating that a valid response is not available without submitting a request for the other information to the first partition.

33. A computing device comprising partitions, wherein each partition comprises:

a set of registers, normally readable by other partitions, and addressable memory, the set of registers comprising at least one bounds register arranged to give the location of a shared memory window, and an associated sharing set register within its partition arranged to specify other partitions authorized to read the shared memory window; and

a memory controller that in operation permits the shared memory window to be read by partitions specified in the associated sharing set register as being authorized to read that shared memory window and denies other access to the addressable memory from outside the partition.

34. A device for use as a partition in a partitioned multiprocessor system, the device comprising at least a processor, addressable memory, and at least one register defining a local address area, the at least one register including at least one sharing set register specifying which of a plurality of other partitions are permitted to read the at least one accessible local address area, and being arrangeable in use to:

make the at least one register readable to other partitions;

make at least one accessible local address area defined by the at least one register readable to other partitions;

maintain address areas other than the at least one accessible local address area and prevent access to those other address areas from other partitions;

maintain information giving the location of at least one remote register in another partition;

obtain from the at least one remote register the address of at least one accessible remote address area in the other partition accessible to the processor;

read and respond to data in the at least one accessible remote address area; and

place data for a processor in the other partition in the at least one accessible local address area.

35. A device according to claim 34, which is arranged in use to make the at least one register and the at least one accessible local address area readable to other partitions but to prevent other partitions from writing to the at least one register and the at least one accessible local address area.

36. A device according to claim 34, wherein the at least one accessible local address area comprises at least two accessible local address areas, the at least one sharing set register comprises at least two sharing set registers, and each of the sharing set registers specifies which other partitions are permitted to read a respective one of the accessible local address areas.

37. A device according to claim 36, wherein each sharing set register specifies a different single other partition that is permitted to read the respective accessible local address area.

38. A device according to claim 34, wherein the at least one sharing set register comprises a sharing set register specifying two or more other partitions that are permitted to read an accessible local address area common to said two or more other partitions.