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Bandwidth limiting on generated PCIe packets from debug source

  • US 8,898,359 B2
  • Filed: 02/26/2013
  • Issued: 11/25/2014
  • Est. Priority Date: 06/20/2012
  • Status: Expired due to Fees
First Claim
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1. A method for regulating bandwidth, comprising:

  • receiving at a memory, debug data packets and functional data packets for transmittal on a shared bus;

    transmitting, via the shared bus, the functional data packets and one or more of the debug data packets according to a predefined ratio of debug data packets to functional data packets maintained by an arbiter;

    dropping one or more of the received debug data packets in the memory;

    maintaining a count of the one or more dropped debug data packets;

    updating, by the arbiter, the predefined ratio based on the count; and

    using the updated predefined ratio to transmit the functional data packets and one or more of the debug data packets on the shared bus.

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