Low latency data transfer between clock domains operated in various synchronization modes

• US 8,898,503 B2
• Filed: 11/07/2013
• Issued: 11/25/2014
• Est. Priority Date: 11/15/2012
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dreps, Daniel M., Ferraiolo, Frank D., Harrer, Hubert, Mak, Pak-kin, Tong, Ching-Lung L., Webel, Tobias, Weiss, Ulrich
• Primary Examiner(s): SHIN, CHRISTOPHER B
• Application Number:
  US14/073,978
• Publication Number:
  US 20140136737A1
• Time in Patent Office: 383 Days
• Field of Search: 713500-501, 713/600, 710/52, 710/58, 710/61
• US Class Current: 713/501
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 5/16 Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Abstract

Transferring data from a first clock domain to a second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency. The first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and in an asynchronous mode when the variable frequency is lower than the fixed frequency. A first buffer and a second buffer are used for a data transfer from the first clock domain to the second clock domain. The second clock domain comprises a multiplexor connected to the first buffer and the second buffer. The multiplexor forwards data from the first buffer further into the second clock domain in the synchronous mode and from the second buffer into the second clock domain in the asynchronous mode.

Claims

1. A method of transferring data from a first clock domain to a second clock domain, the method comprising:

writing the data from the first clock domain into a first buffer for a data transfer from the first clock domain to the second clock domain and into a second buffer for the data transfer from the first clock domain to the second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency not exceeding the clock frequency of the second clock domain, the first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and the first clock domain and the second clock domain operate in an asynchronous mode when the variable frequency is lower than the fixed frequency, wherein the first buffer has a first time delay for the data transfer from the first clock domain to the second clock domain, wherein the second buffer has a second time delay for the data transfer from the first clock domain to the second clock domain, the second delay time is longer than the first delay time, the first buffer and the second buffer being connected in parallel to each other and in series with the first clock domain and the second clock domain, wherein the first and the second buffers being connected to a multiplexor in the second clock domain;

forwarding the data from the first buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the synchronous mode; and

forwarding the data from the second buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the asynchronous mode.

2. The method of claim 1, wherein the multiplexor has a mux input port for receiving a first mux command to forward the data from the first buffer into the second clock domain and a second mux command to forward the data from the second buffer into the second clock domain, wherein the first clock domain comprises a first plurality of logic devices for generating the variable clock frequency and a frequency synchronization with the fixed clock frequency in the synchronous mode, wherein the first plurality of logic devices comprises a first sync on/off input port for receiving a first sync on command to switch on the frequency synchronization with the fixed clock frequency and a first sync off command to switch off the frequency synchronization with the fixed clock frequency, wherein the first plurality of logic devices comprises a set frequency input port for receiving a set frequency command to set the variable frequency to a frequency value, wherein the second clock domain comprises a second plurality of logic devices for generating the fixed frequency and the frequency synchronization with the variable clock frequency in the synchronous mode, wherein the second plurality of logic devices comprises a second sync on/off input port for receiving a second sync on command for switching on the frequency synchronization with the variable clock frequency and a second sync off command for switching off the frequency synchronization with the variable clock frequency, wherein a transition from the synchronous mode to the asynchronous mode comprises:

switching the multiplexor to forward the data from the second buffer into the second clock domain, wherein the multiplexor receives the second mux command via the mux input port;

switching off the frequency synchronization, wherein the first plurality of logic devices receives the first sync off command via the first sync on/off input port and the second plurality of logic devices receives the second sync off command via the second sync on/off input port; and

decreasing the variable clock frequency, wherein the first plurality of logic devices receives the set frequency command via the set frequency input port, wherein the frequency value is lower than the fixed clock frequency.

3. The method of claim 1, wherein the multiplexor has a mux input port for receiving a first mux command to forward the data from the first buffer into the second clock domain and a second mux command to forward the data from the second buffer into the second clock domain, wherein the first clock domain comprises a first plurality of logic devices for generating the variable clock frequency and a frequency synchronization with the fixed clock frequency in the synchronous mode, wherein the first plurality of logic devices comprises a first sync on/off input port for receiving a first sync on command to switch on the frequency synchronization with the fixed clock frequency and a first sync off command to switch off the frequency synchronization with the fixed clock frequency, wherein the first plurality of logic devices comprises a set frequency input port for receiving a set frequency command to set the variable frequency to a frequency value, wherein the second clock domain comprises a second plurality of logic devices for generating the fixed frequency and the frequency synchronization with the variable clock frequency in the synchronous mode, wherein the second plurality of logic devices comprises a second sync on/off input port for receiving a second sync on command for switching on the frequency synchronization with the variable clock frequency and a second sync off command for switching off the frequency synchronization with the variable clock frequency, wherein a transition from the asynchronous mode to the synchronous mode comprises:

increasing the variable clock frequency, wherein the first plurality of logic devices receives the set frequency command via the set frequency input port, wherein the frequency value is equal to the fixed frequency;

switching on the frequency synchronization, wherein the first plurality of logic devices receives the first sync on command via the first sync on/off input port and the second plurality of logic devices receives the second sync on command via the second sync on/off input port; and

switching the multiplexor to forward the data from the first buffer into the second clock domain, wherein the multiplexor receives the first mux command via the mux input port.

4. The method of claim 1, wherein the first clock domain is a CPU clock domain and the second clock domain is an I/O clock domain.

5. The method of claim 3, wherein the first plurality of logic devices comprises a digital phase lock loop for generation of the variable clock frequency and the second plurality of logic devices comprises a tank phase lock loop for generation of the fixed clock frequency.

6. The method of claim 1, wherein the first buffer and the second buffer are a first-in first-out type buffers.

7. A computer system comprising:

a first clock domain and a second clock domain, wherein the second clock domain has a fixed clock frequency, the first clock domain has a variable clock frequency not exceeding the clock frequency of the second clock domain, the first clock domain and the second clock domain operating in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, the first clock domain and the second clock domain operating in an asynchronous mode when the variable frequency is lower than the fixed frequency;

a first buffer and a second buffer for a data transfer from the first clock domain to the second clock domain, the first buffer having a first delay time for the data transfer from the first clock domain to the second clock domain, the second buffer having a second delay time for the data transfer from the first clock domain to the second clock domain, the second delay time being longer than the first delay time, the first buffer and the second buffer being connected in parallel to each other and in series with the first clock domain and the second clock domain, wherein the first buffer and the second buffer are connected to a multiplexor in the second clock domain, said multiplexor forwarding data transferred by the first buffer in the synchronous mode or the data transferred by the second buffer in the asynchronous mode.

8. The computer system of claim 7, wherein the multiplexor has a mux input port for receiving a first mux command for forwarding the data from the first buffer into the second clock domain and a second mux command for forwarding the data from the second buffer into the second clock domain.

9. The computer system of claim 7, wherein:

the first clock domain comprises a first plurality of logic devices for generating the variable clock frequency and a frequency synchronization with the fixed clock frequency in the synchronous mode; and

the first plurality of logical devices comprises a first sync on/off input port for receiving a first sync on command to switch on the frequency synchronization and a first sync off command to switch off the frequency synchronization, the first plurality of logical devices comprises a set frequency input port to set the variable clock frequency to a frequency value.

10. The computer system of claim 9, wherein the first plurality of logic devices comprises a digital phase look loop for generation of the variable clock frequency.

11. The computer system of claim 7, wherein:

the second clock domain comprises a second plurality of logic devices for generating the fixed clock frequency and a frequency synchronization with the variable clock frequency in the synchronous mode; and

the second plurality of logical devices comprises a second sync on/off input port for receiving a second sync on command to switch on the frequency synchronization and a second sync off command to switch off the frequency synchronization.

12. The computer system of claim 11, wherein the second plurality of logic devices comprises a tank phase lock loop for generation of the fixed clock frequency.

13. The computer system of claim 7, wherein the first clock domain is a CPU clock domain and the second clock domain is an I/O clock domain.

14. The computer system of claim 7, wherein the first buffer is a first-in first-out type buffer.

15. The computer system of claim 7, wherein the second buffer is a first-in first-out type buffer.

16. A computer program product for transferring data from a first clock domain to a second clock domain, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method comprising;

writing the data from the first clock domain into a first buffer for a data transfer from the first clock domain to the second clock domain and into a second buffer for the data transfer from the first clock domain to the second clock domain, wherein the second clock domain has a fixed clock frequency, and the first clock domain has a variable clock frequency not exceeding the clock frequency of the second clock domain, the first clock domain and the second clock domain operate in a synchronous mode when the variable clock frequency is equal to the fixed clock frequency, and the first clock domain and the second clock domain operate in an asynchronous mode when the variable frequency is lower than the fixed frequency, wherein the first buffer has a first time delay for the data transfer from the first clock domain to the second clock domain, wherein the second buffer has a second time delay for the data transfer from the first clock domain to the second clock domain, the second delay time is longer than the first delay time, the first buffer and the second buffer being connected in parallel to each other and in series with the first clock domain and the second clock domain, wherein the first and the second buffers being connected to a multiplexor in the second clock domain;

forwarding the data from the first buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the synchronous mode; and

forwarding the data from the second buffer via the multiplexor into the second clock domain based on the first clock domain and the second clock domain operating in the asynchronous mode.

17. The computer program product of claim 16, wherein the multiplexor has a mux input port for receiving a first mux command to forward the data from the first buffer into the second clock domain and a second mux command to forward the data from the second buffer into the second clock domain, wherein the first clock domain comprises a first plurality of logic devices for generating the variable clock frequency and a frequency synchronization with the fixed clock frequency in the synchronous mode, wherein the first plurality of logic devices comprises a first sync on/off input port for receiving a first sync on command to switch on the frequency synchronization with the fixed clock frequency and a first sync off command to switch off the frequency synchronization with the fixed clock frequency, wherein the first plurality of logic devices comprises a set frequency input port for receiving a set frequency command to set the variable frequency to a frequency value, wherein the second clock domain comprises a second plurality of logic devices for generating the fixed frequency and the frequency synchronization with the variable clock frequency in the synchronous mode, wherein the second plurality of logic devices comprises a second sync on/off input port for receiving a second sync on command for switching on the frequency synchronization with the variable clock frequency and a second sync off command for switching off the frequency synchronization with the variable clock frequency, wherein a transition from the synchronous mode to the asynchronous mode comprises:

switching the multiplexor to forward the data from the second buffer into the second clock domain, wherein the multiplexor receives the second mux command via the mux input port;

switching off the frequency synchronization, wherein the first plurality of logic devices receives the first sync off command via the first sync on/off input port and the second plurality of logic devices receives the second sync off command via the second sync on/off input port; and

decreasing the variable clock frequency, wherein the first plurality of logic devices receives the set frequency command via the set frequency input port, wherein the frequency value is lower than the fixed clock frequency.

18. The computer program product of claim 16, wherein the multiplexor has a mux input port for receiving a first mux command to forward the data from the first buffer into the second clock domain and a second mux command to forward the data from the second buffer into the second clock domain, wherein the first clock domain comprises a first plurality of logic devices for generating the variable clock frequency and a frequency synchronization with the fixed clock frequency in the synchronous mode, wherein the first plurality of logic devices comprises a first sync on/off input port for receiving a first sync on command to switch on the frequency synchronization with the fixed clock frequency and a first sync off command to switch off the frequency synchronization with the fixed clock frequency, wherein the first plurality of logic devices comprises a set frequency input port for receiving a set frequency command to set the variable frequency to a frequency value, wherein the second clock domain comprises a second plurality of logic devices for generating the fixed frequency and the frequency synchronization with the variable clock frequency in the synchronous mode, wherein the second plurality of logic devices comprises a second sync on/off input port for receiving a second sync on command for switching on the frequency synchronization with the variable clock frequency and a second sync off command for switching off the frequency synchronization with the variable clock frequency, wherein a transition from the asynchronous mode to the synchronous mode comprises:

increasing the variable clock frequency, wherein the first plurality of logic devices receives the set frequency command via the set frequency input port, wherein the frequency value is equal to the fixed frequency;

switching on the frequency synchronization, wherein the first plurality of logic devices receives the first sync on command via the first sync on/off input port and the second plurality of logic devices receives the second sync on command via the second sync on/off input port; and

switching the multiplexor to forward the data from the first buffer into the second clock domain, wherein the multiplexor receives the first mux command via the mux input port.

19. The computer program product of claim 16, wherein the first clock domain is a CPU clock domain and the second clock domain is an I/O clock domain.

20. The computer program product of claim 18, wherein the first plurality of logic devices comprises a digital phase lock loop for generation of the variable clock frequency and the second plurality of logic devices comprises a tank phase lock loop for generation of the fixed clock frequency.