Methods, data storage devices and systems having variable size ECC page size

• US 8,898,548 B1
• Filed: 08/24/2012
• Issued: 11/25/2014
• Est. Priority Date: 08/24/2012
• Status: Active Grant

• Current Assignee: JP Morgan Chase Bank, N.A. (JP Morgan Chase & Co)
• Original Assignee: Western Digital Technologies Incorporated (Western Digital Corporation)
• Inventors: Mullendore, Rodney N., Danilak, Radoslav, Tomlin, Andrew J., Jones, Justin
• Primary Examiner(s): TRIMMINGS, JOHN P
• Application Number:
  US13/594,696
• Time in Patent Office: 823 Days
• Field of Search: None
• US Class Current: 714/774
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: H03M 13/353 Adaptation to the channel

Abstract

A data storage device may comprise an array of flash memory devices and a controller coupled thereto, configured to program and read data from the array responsive to received data access commands. The array may comprise a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of which comprising an integer number of one or more error correcting code pages (E-Pages), at least some of which comprising a data portion and an error correction code (ECC) portion. The controller may be configured to store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some being unaligned with boundaries of the E-Pages; and to adjust, in at least one of the blocks, the size of the ECC portion and correspondingly adjust the size of the data portion of the E-Pages.

Claims

1. A data storage device, comprising:

an array of flash memory devices; and

a controller coupled to the array of memory devices and configured to program and read data from the array of flash memory devices responsive to data access commands from a host, wherein the array of flash memory devices comprises;

a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code pages (E-Pages), at least some of the E-Pages comprising a data portion and an error correction code (ECC) portion;

wherein the controller is configured to;

store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some of the plurality of L-Pages being unaligned with boundaries of the E-Pages; and

adjust, in at least one of the F-Pages, a size of the ECC portion and correspondingly adjust a size of the data portion of one or more E-Pages of the at least one F-Page, wherein the controller is further configured to decrease the size of the data portion by an amount that the size of the ECC portion has been increased.

2. The data storage device of claim 1, wherein each E-Page is configured to store a minimum amount of data readable by the controller.

3. The data storage device of claim 1, wherein the controller is further configured to adjust a size of the ECC portion and to correspondingly adjust a size of the data portion of the one or more E-Pages of the at least one F-Page in accordance with one of a plurality of ECC profiles.

4. The data storage device of claim 3, wherein at least some of the plurality of ECC profiles are configured to correct a different amount of data stored in the E-Page.

5. The data storage device of claim 3, wherein the controller is further configured to determine which of the plurality of ECC profiles is to be applied across F-Pages of a block of the plurality of blocks, at a time of programming the block.

6. The data storage device of claim 3, wherein the controller is further configured to apply different ones of the plurality of ECC profiles to different ones of the plurality of blocks.

7. The data storage device of claim 3, wherein the controller is further configured to determine which of the plurality of ECC profiles to apply to a block of the plurality of blocks, an F-Page of the plurality of F-Pages or an E-Page of the plurality of E-Pages, at runtime.

8. The data storage device of claim 3, wherein the controller is further configured to determine which of the plurality of ECC profiles to apply to a block, an F-Page or an E-Page based on an error rate.

9. The data storage device of claim 8, wherein the error rate is based on a prior occurrence of ECC errors within the block, the F-Page or the E-Page.

10. The data storage device of claim 3, wherein the controller is further configured to determine which of the plurality of ECC profiles to apply to a block based on a program/erase (PE) count of the block.

11. The data storage device of claim 3, wherein the controller is further configured to read L-Pages that span across blocks and to accommodate two or more of the plurality of ECC profiles within a single read operation involving an L-Page.

12. The data storage device of claim 3, wherein one of the plurality of ECC profiles is configured, when used in an invalid F-Page, to cause the controller to skip the invalid F-Page when programming.

13. The data storage device of claim 1, wherein the controller is further configured to increase a size of the ECC portion and correspondingly decrease a size of the data portion of one or more of the E-Pages of a block when a program/erase (PE) count of the block reaches a pre-determined threshold.

14. The data storage device of claim 1, wherein the controller is further configured to increase overprovisioning of the storage device by decreasing a size of the ECC portion and correspondingly increasing a size of the data portion of E-Pages of a block when a program/erase (PE) count of the block is below a pre-determined threshold.

15. The data storage device of claim 1, wherein the controller is further configured to adjust the size of the ECC portion based at least in part on a condition of the block in which the at least one F-Page resides.

16. The data storage device of claim 15, wherein the condition is based at least one of:

an ECC error rate, flash error information, a temperature, a dwell time, and internal flash state information.

17. The data storage device of claim 1, wherein the controller is further configured to adjust at least one of:

(1) the size of the ECC portion, and (2) the size of the data portion, based on at least one of;

host-provided meta data and overall free space in the data storage device.

18. A method of controlling an array of flash memory devices responsive to data access commands from a host, comprising:

receiving a host command to store host data in one or more of a plurality of blocks of the array of flash memory devices, each of the plurality of blocks comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code (ECC) pages (E-Pages), at least some of the E-Pages comprising a data portion and an ECC portion;

selecting an ECC profile of a plurality of ECC profiles to apply to the one or more of the plurality of blocks, F-Pages or E-Pages to which the host data is to be stored;

storing the host data in one or more logical pages (L-Pages);

programming the one or more of L-Pages into the data portion of one or more of the plurality of E-Pages and generating an ECC code to be stored in the ECC portion of one or more of the plurality of E-Pages according to the selected ECC profile; and

adjusting, in at least one of the F-Pages, a size of the ECC portion and correspondingly adjusting a size of the data portion of one or more E-Pages of the at least one F-Page according to a new ECC profile, wherein adjusting comprises decreasing the size of the data portion by an amount that the size of the ECC portion has been increased.

19. The method of claim 18, wherein each E-Page is configured to store a minimum amount of data readable by the controller.

20. The method of claim 18, wherein the adjusting further comprising selecting the new profile from the plurality of ECC profiles.

21. The method of claim 18, wherein at least some of the plurality of ECC profiles are configured to correct a different amount of data stored in the E-Page.

22. The method of claim 18, wherein selecting comprises selecting a first one of the plurality of ECC profiles to program F-Pages of a first block of the plurality of blocks and selecting a second one of the plurality of ECC profiles to program F-Pages of a second block of the plurality of blocks.

23. The method of claim 18, further comprising increasing a size of the ECC portion and correspondingly decreasing a size of the data portion of one or more of the E-Pages of a block of the plurality of blocks when a program/erase (PE) count of the block reaches a predetermined threshold.

24. The method of claim 18, further comprising increasing overprovisioning of the array of flash memory devices by decreasing a size of the ECC portion and correspondingly increasing a size of the data portion of E-Pages of a block of the plurality of blocks when a program/erase (PE) count of the block is below a predetermined threshold.

25. The method of claim 18, wherein adjusting comprises adjusting based at least in part upon a condition of the block in which the at least one F-Page resides.

26. The method of claim 25, wherein the condition is based at least one of:

an ECC error rate, flash error information, a temperature, a dwell time, and internal flash state information.

27. The method of claim 18, wherein adjusting comprises adjusting at least one of:

(1) the size of the ECC portion, and (2) the size of the data portion, based on at least one of;

host-provided meta data and overall free space in the data storage device.

28. The method of claim 18, wherein selecting an ECC profile to apply comprises selecting based on an error rate.

29. The method of claim 28, wherein the error rate is based on a prior occurrence of ECC errors within a block of the plurality of blocks, an F-Page of the plurality of F-Pages or an E-Page of the plurality of E-Pages.

30. The method of claim 18, wherein selecting comprises selecting based on a PE count of a block of the plurality of blocks.

31. The method of claim 18, wherein one of the plurality of profiles is configured, when used in an invalid F-Page, to the invalid F-Page to be skipped when a programming operation is performed in the block in which the invalid F-Page resides.

32. The method of claim 18, further comprising compressing the host data in the L-Pages before programming them into the data portion of one or more of the plurality of E-Pages.

33. The method of claim 18, further comprising maintaining the selected ECC profile for a block of the plurality of blocks until at least a garbage collection of the block has occurred.

34. The method of claim 18, further comprising creating a concatenated E-Page from a first E-Page and a second E-Page, the concatenated E-Page comprising an ECC portion and a data portion, the data portion having a size equal to a sum of the sizes of the data portions of the first and second E-Pages plus the size of the ECC portion.

35. The method of claim 18, further comprising creating two E-Pages from a single E-Page, each of the two E-Pages having an ECC portion and a data portion, the data portion having a size equal to a difference of the size of a data portion of the single E-Page and half of the size of an ECC portion of the single E-Page.

36. A solid state drive controller, comprising:

a buffer configured to couple to an array of flash memory devices; and

a processor coupled to the buffer, the processor being configured to program and read data from the array of flash memory devices responsive to data access commands from a host, the array of flash memory devices comprising a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code pages (E-Pages), at least some of the E-Pages comprising a data portion and an error correction code (ECC) portion,

wherein the processor is further configured to;

store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages; and

adjust, in at least one of the F-Pages, a size of the ECC portion and correspondingly adjust a size of the data portion of the E-Pages of the one or more E-Pages of the at least one F-Page,

wherein the processor is further configured to decrease the size of the data portion by an amount that the size of the ECC portion has been increased.

37. The solid state drive controller of claim 36, wherein the processor is further configured to carry out a first read of a first data configured according to a first one of a plurality of different ECC profiles and to carry out a second read of a second data configured according to a second one of the plurality of different ECC profiles and to store the read first and second data in the buffer.

38. The solid state drive controller of claim 36, wherein each E-Page is configured to store a minimum amount of data readable by the processor.

39. The solid state drive controller of claim 36, wherein the processor is further configured to adjust a size of the ECC portion and to correspondingly adjust a size of the data portion of the E-Pages of the block in accordance with one of a plurality of ECC profiles.

40. The solid state drive controller of claim 39, wherein at least some of the plurality of ECC profiles are configured to correct a different amount of data stored in the E-Page.

41. The solid state drive controller of claim 39, wherein the processor is further configured to determine which of the plurality of ECC profiles is to be applied across F-Pages of a block of the plurality of blocks, at a time of programming the block.

42. The solid state drive controller of claim 41, wherein the processor is further configured to apply different ECC profiles to different ones of the plurality of blocks or to different ones of the plurality of F-Pages of a block of the plurality of blocks.

43. The solid state drive controller of claim 39, wherein the processor is further configured to determine which of the plurality of ECC profiles to apply to a block of the plurality of blocks, an F-Page of the plurality of F-Pages or an E-Page of the plurality of E-Pages, at runtime.

44. The solid state drive controller of claim 39, wherein the processor is further configured to determine which of the plurality of ECC profiles to apply to a block of the plurality of blocks, an F-Page of the plurality of F-Pages or an E-Page of the plurality of E-Pages, based on an error rate.

45. The solid state drive controller of claim 44, wherein the error rate is based on a prior occurrence of ECC errors within the block.

46. The solid state drive controller of claim 39, wherein the processor is further configured to read L-Pages that span across blocks and to accommodate two or more of the plurality of ECC profiles within a single read operation involving an L-Page.

47. The solid state drive controller of claim 36, wherein one of the plurality of ECC profiles is configured, when used in an invalid E-Page, such that the processor skips the invalid F-Page when programming.

48. The solid state drive controller of claim 36, wherein the processor is further configured to increase a size of the ECC portion and correspondingly decrease a size of the data portion of one or more of the E-Pages when a program/erase (PE) count reaches a predetermined threshold.

49. The solid state drive controller of claim 36, wherein the processor is further configured to increase overprovisioning by decreasing a size of the ECC portion and correspondingly increasing a size of the data portion of E-Pages of a block when a program/erase (PE) count of the block is below a predetermined threshold.

50. The solid state drive controller of claim 36, wherein the processor is further configured to adjust the size of the ECC portion based at least in part on a condition of the block in which the at least one F-Page resides.

51. The solid state drive controller of claim 50, wherein the condition is based at least one of:

an ECC error rate, flash error information, a temperature, a dwell time, and internal flash state information.

52. The solid state drive controller of claim 36, wherein the processor is further configured to adjust at least one of:

(1) the size of the ECC portion, and (2) the size of the data portion, based on at least one of;

host-provided meta data and overall free space in the data storage device.

53. The solid state drive controller of claim 36, wherein the processor is further configured to determine which of the plurality of ECC profiles to apply to a block of the plurality of blocks based on a PE count of the block.

54. A data storage device, comprising:

an array of flash memory devices; and

a controller coupled to the array of memory devices and configured to program and read data from the array of flash memory devices responsive to data access commands from a host, wherein the array of flash memory devices comprises;

a plurality of blocks, each comprising a plurality of flash pages (F-Pages), each of the plurality of F-Pages comprising an integer number of one or more error correcting code pages (E-Pages), at least some of the E-Pages comprising a data portion and an error correction code (ECC) portion;

wherein the controller is configured to;

store a plurality of logical pages (L-Pages) in one or more of the plurality of E-Pages, at least some of the plurality of L-Pages being unaligned with boundaries of the E-Pages; and

decrease a size of the data portion of one or more E-Pages of the at least one F-Page by an amount that a size of the ECC portion has been increased; and

wherein, one of the plurality of blocks comprises;

a first E-Page having an ECC portion of a first size; and

a second E-Page having an ECC portion of a second size, wherein the second size is different from the first size, wherein the second size is selected based on a location of the second E-Page in the block.