Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor

• US 8,898,768 B2
• Filed: 03/15/2013
• Issued: 11/25/2014
• Est. Priority Date: 01/26/2010
• Status: Active Grant

• Current Assignee: Frampton E. Ellis
• Original Assignee: Frampton E. Ellis
• Inventors: Ellis, Frampton E.
• Primary Examiner(s): SIMITOSKI, MICHAEL J
• Application Number:
  US13/815,814
• Publication Number:
  US 20130232564A1
• Time in Patent Office: 620 Days
• Field of Search: 726/11, 726/22, 726/30, 713/153, 713/154, 713/194
• US Class Current: 726/11
• CPC Class Codes: G06F 11/2043 where the redundant components share a common memory address space
• CPC Class Codes: G06F 21/50 Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
• CPC Class Codes: G06F 21/71 to assure secure computing or processing of information
• CPC Class Codes: G06F 21/85 interconnection devices, e.g. bus-connected or in-line devices
• CPC Class Codes: H04L 63/02 for separating internal from external traffic, e.g. firewalls
• CPC Class Codes: H04L 63/0209 Architectural arrangements, e.g. perimeter networks or demilitarized zones

Abstract

A computer or microchip comprising a central controller that connected by a secure control bus with the other parts of the computer or microchip, including a volatile random access memory (RAM) located in a portion of the computer or microchip that is connected to a network. The secure control bus is isolated from any input from the network and provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM). The direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM) and includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and a microprocessor having a connection for the network.

Claims

1. A computer or microchip, comprising:

a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with the other parts of the computer or microchip, including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has a connection for a network;

the secure control bus is isolated from any input from the network;

the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM);

the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and

the direct preemptive control also includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network.

2. The computer or microchip according to claim 1, wherein the secure control bus includes a first on/off switch that is located between the central controller and the volatile random access memory (RAM).

3. The computer or microchip according to claim 2, wherein the secure control bus includes a second on/off switch that is located between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network.

4. The computer or microchip according to claim 3, wherein the secure control bus has a configuration such that the first on/off switch is closed and the second on/off switch is open, so that the central controller is connected to and has direct preemptive control over the volatile random access memory (RAM), which is disconnected from the network.

5. The computer or microchip according to claim 4, wherein the computer or microchip includes a public unit having a connection for the Internet and at least one private unit;

the central controller is located in said at least one private unit and the volatile random access memory (RAM) is located in the public unit.

6. The computer or microchip according to claim 4, wherein the central controller using the secure control bus is configured to erase the volatile random access memory (RAM).

7. The computer or microchip according to claim 6, wherein the central controller using the secure control bus is configured to erase of the volatile random access memory (RAM) by power interruption to the volatile random access memory (RAM).

8. The computer or microchip according to claim 4, wherein the central controller using the secure control bus is configured to transmit data and/or code to the volatile random access memory (RAM).

9. The computer or microchip according to claim 3, wherein the secure control bus has a configuration such that the first on/off switch is open and the second on/off switch is closed, so that the volatile random access memory (RAM) is disconnected from the central controller and connected to said microprocessor having a connection for the network.

10. The computer or microchip according to claim 3, wherein at least the first on/off switch is located in at least one access barrier or firewall that is located between the public unit and the private unit.

11. The computer or microchip according to claim 10, wherein at least the volatile random access memory (RAM) is located in at least one access barrier or firewall that is located between the public unit and the private unit.

12. The computer or microchip according to claim 11, wherein at least the second on/off switch is located in at least one access barrier or firewall that is located between the public unit and the private unit.

13. The computer or microchip according to claim 1, further comprising:

one or more buffer zones, each excluding circuitry;

two or more zones, each including circuitry; and

the one or more buffer zones forming one or more boundaries separating the zones including circuitry.

14. The computer or microchip according to claim 1, wherein the secure control bus is not connected to the network.

15. A computer or microchip, comprising:

a central controller of the computer or microchip, including a master controlling device or a master control unit;

a public unit with a connection for connection to the Internet and at least one private unit that is not connected to the Internet;

the central controller is located in said at least one private unit;

at least one lock mechanism is located between the public unit and the at least one private unit and includes at least one volatile random access memory (RAM) and at least one bus; and

the at least one bus includes at least a first on/off switch between the private unit and the at least one volatile random access memory (RAM) and at least a second on/off switch between the at least one volatile random access memory (RAM) and the public unit.

16. The computer or microchip according to claim 15, wherein at least one access barrier or firewall is located between the public unit and the at least one private unit and said at least one access barrier or firewall separates the public unit from the at least one private unit, and includes the at least one lock mechanism.

17. The computer or microchip according to claim 16, wherein the lock mechanism has a configuration such that that the first on/off switch is closed and the second on/off switch is open, so that the central controller is connected to and has direct preemptive control over the volatile random access memory (RAM), which is disconnected from the public unit.

18. The computer or microchip according to claim 17, wherein the central controller using the bus is configured to erase the volatile random access memory (RAM).

19. The computer or microchip according to claim 18, wherein the central controller using the bus is configured to erase the volatile random access memory (RAM) by power interruption to the volatile random access memory (RAM).

20. The computer or microchip according to claim 17, wherein the central controller using the bus is configured to transmit data and/or code to the volatile random access memory (RAM).

21. The computer or microchip according to claim 16, wherein the secure control bus has a configuration such that that the first on/off switch is open and the second on/off switch is closed, so that the volatile random access memory (RAM) is disconnected from the central controller and connected to the public unit.