Computer or microchip with a secure control bus connecting a central controller to volatile RAM and the volatile RAM to a network-connected microprocessor
First Claim
1. A computer or microchip, comprising:
- a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with the other parts of the computer or microchip, including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has a connection for a network;
the secure control bus is isolated from any input from the network;
the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM);
the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and
the direct preemptive control also includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network.
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Abstract
A computer or microchip comprising a central controller that connected by a secure control bus with the other parts of the computer or microchip, including a volatile random access memory (RAM) located in a portion of the computer or microchip that is connected to a network. The secure control bus is isolated from any input from the network and provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM). The direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM) and includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and a microprocessor having a connection for the network.
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Citations
21 Claims
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1. A computer or microchip, comprising:
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a central controller of the computer or microchip, including a master controlling device or a master control unit, having a connection by a secure control bus with the other parts of the computer or microchip, including at least a volatile random access memory (RAM) located in a portion of the computer or microchip that has a connection for a network; the secure control bus is isolated from any input from the network; the secure control bus has a configuration by which it provides and ensures direct preemptive control by the central controller over the volatile random access memory (RAM); the direct preemptive control includes transmission of data and/or code to the volatile random access memory (RAM) or erasure of data and/or code in the volatile random access memory (RAM); and the direct preemptive control also includes control of the connection between the central controller and the volatile random access memory (RAM) and between the volatile random access memory (RAM) and at least one microprocessor that has a connection for the network. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A computer or microchip, comprising:
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a central controller of the computer or microchip, including a master controlling device or a master control unit; a public unit with a connection for connection to the Internet and at least one private unit that is not connected to the Internet; the central controller is located in said at least one private unit; at least one lock mechanism is located between the public unit and the at least one private unit and includes at least one volatile random access memory (RAM) and at least one bus; and the at least one bus includes at least a first on/off switch between the private unit and the at least one volatile random access memory (RAM) and at least a second on/off switch between the at least one volatile random access memory (RAM) and the public unit. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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Specification