Array substrate and manufacturing method thereof

• US 8,900,900 B2
• Filed: 02/21/2013
• Issued: 12/02/2014
• Est. Priority Date: 11/19/2012
• Status: Active Grant

• Current Assignee: AU Optronics Corporation
• Original Assignee: AU Optronics Corporation
• Inventors: Chen, Ming-Yao, Chen, Pei-Ming
• Primary Examiner(s): GHYKA, ALEXANDER G
• Application Number:
  US13/772,346
• Publication Number:
  US 20140138714A1
• Time in Patent Office: 649 Days
• Field of Search: 438/34, 438/128
• US Class Current: 438/34
• CPC Class Codes: H01L 21/77 Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate electrically programmable read-only memories or multistep manufacturing processes therefor H10B69/00
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1248 with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask

Abstract

A manufacturing method of an array substrate includes the following steps. A substrate having pixel region and a peripheral region is provided. A plurality of pixel structures are formed in the pixel region, wherein at least one of the pixel structures is formed by the following steps. A gate electrode, a gate insulating layer, and a source electrode and a drain electrode are formed. A patterned semiconductor layer including a first semiconductor pattern and a second semiconductor pattern is formed. The second semiconductor pattern covers a portion of the drain electrode. A first passivation layer is formed. The first passivation layer has a first opening exposing a portion of the second semiconductor pattern. A transparent conductive pattern is formed on the first passivation layer, and the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

Claims

1. A manufacturing method of an array substrate comprising:

providing a substrate having a pixel region and a peripheral region adjacent to the pixel region;

forming a plurality of pixel structures in the pixel region, wherein steps of forming at least one of the pixel structures comprise;

forming a patterned first metal layer, a gate insulating layer, and a patterned second metal layer on the substrate, wherein the patterned first metal layer comprises a gate electrode, and the patterned second metal layer comprises a source electrode and a drain electrode ;

forming a patterned semiconductor layer on the substrate, wherein the patterned semiconductor layer comprises a first semiconductor pattern and a second semiconductor pattern, the first semiconductor pattern is substantially corresponding to the gate electrode and covers a portion of the source electrode and a portion of the drain electrode, and the second semiconductor pattern covers a portion of the drain electrode;

forming a first passivation layer on the substrate, wherein the first passivation layer has a first opening exposing a portion of the second semiconductor pattern; and

forming a first patterned transparent conductive layer on the first passivation layer, wherein the first patterned transparent conductive layer comprises a transparent conductive pattern, the transparent conductive pattern is electrically connected to the second semiconductor pattern through the first opening.

2. The manufacturing method of the array substrate of claim 1, wherein the patterned semiconductor layer comprises an oxide semiconductor layer.

3. The manufacturing method of the array substrate of claim 1, wherein the first semiconductor pattern and the second semiconductor pattern are physically spaced apart from each other.

4. The manufacturing method of the array substrate of claim 1, wherein the first passivation layer comprises an insulating layer and a planarization layer.

5. The manufacturing method of the array substrate of claim 1, further comprising:

forming a second passivation layer on the first passivation layer; and

forming a second patterned transparent conductive layer on the second passivation layer, the second patterned transparent conductive layer having a plurality of openings.

6. The manufacturing method of the array substrate of claim 1, wherein the first patterned transparent conductive layer further comprises a common electrode electrically isolated from the transparent conductive pattern.

7. The manufacturing method of the array substrate of claim 6, further comprising:

forming a second passivation layer on the first patterned transparent conductive layer;

forming a second opening exposing a portion of the transparent conductive pattern in the second passivation layer; and

forming a second patterned transparent conductive layer on the second passivation layer, wherein the second patterned transparent conductive layer is electrically connected to the transparent conductive pattern through the second opening, and the second patterned transparent conductive layer has a plurality of openings.

8. The manufacturing method of the array substrate of claim 1, further comprising performing a surface treatment to the second semiconductor pattern before forming the first patterned transparent conductive layer.

9. The manufacturing method of the array substrate of claim 8, wherein the surface treatment comprises a plasma surface treatment.

10. The manufacturing method of the array substrate of claim 1, wherein the patterned second metal layer further comprises a connecting layer disposed in the peripheral region, the patterned semiconductor layer further comprises a third semiconductor pattern disposed on the connecting layer and covering a portion of the connecting layer, the first passivation layer covers a portion of the third semiconductor pattern, and the first passivation layer further has a third opening exposing a portion of the third semiconductor pattern.

11. The manufacturing method of the array substrate of claim 1, wherein the gate electrode, the first semiconductor pattern, the source electrode, and the drain electrode construct a thin film transistor.