Rear-face illuminated solid state image sensors

• US 8,900,910 B2
• Filed: 01/06/2014
• Issued: 12/02/2014
• Est. Priority Date: 11/05/2010
• Status: Active Grant

• Current Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Original Assignee: Adeia Semiconductor Technologies LLC (f/k/a Invensas Corporation) (Adeia Inc.)
• Inventors: Humpston, Giles, Kriman, Moshe
• Primary Examiner(s): ARMAND, MARC ANTHONY
• Application Number:
  US14/148,096
• Publication Number:
  US 20140120650A1
• Time in Patent Office: 330 Days
• Field of Search: 438/66, 438/64, 257/E31.11
• US Class Current: 438/66
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/13024 the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 27/14618 Containers
• CPC Class Codes: H01L 27/14632 Wafer-level processed structures
• CPC Class Codes: H01L 27/14636 Interconnect structures
• CPC Class Codes: H01L 27/14638 Structures specially adapted for transferring the charges across the imager perpendicular to the imaging plane
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14687 Wafer level processing
• CPC Class Codes: H01L 27/14806 Structural or functional details thereof

Abstract

A microelectronic unit includes a semiconductor element having a front surface to which a packaging layer is attached, and a rear surface remote from the front surface. The element includes a light detector including a plurality of light detector element arranged in an array disposed adjacent to the front surface and arranged to receive light through the rear surface. The semiconductor element also includes an electrically conductive contact at the front surface connected to the light detector. The conductive contact includes a thin region and a thicker region which is thicker than the thin region. A conductive interconnect extends through the packaging layer to the thin region of the conductive contact, and a portion of the conductive interconnect is exposed at a surface of the microelectronic unit.

Claims

1. A method of forming a microelectronic unit comprising:

forming a recessed portion extending through a packaging layer attached to a front surface of a semiconductor element and terminating at a thin region of a conductive contact, the conductive contact being disposed at the front surface of the semiconductor element, the semiconductor element having a rear surface remote from the front surface and including a light detector disposed adjacent to the front surface, connected to the conductive contact and aligned with a portion of the rear surface to receive light through the rear surface portion, wherein the light detector includes a plurality of light detector elements arranged in an array, wherein the conductive contact has a first thickness at the thin region and includes a thicker region having a second thickness that is thicker than the first thickness; and

forming a conductive interconnect extending through the recessed portion to connect to the conductive contact at the thin region, at least a portion of the conductive interconnect being exposed at a surface of the microelectronic unit.

2. The method of claim 1, wherein the semiconductor element includes a plurality of microelectronic elements attached together at peripheral edges thereof, each having a respective light detector, wherein the step of forming a recessed portion forms a recessed portion in each of the plurality of microelectronic elements and the step of forming a conductive interconnect forms a conductive interconnect in each of the microelectronic elements, the method further comprising:

severing the semiconductor element with the packaging layer thereon into a plurality of individual microelectronic units.

3. The method of claim 1, wherein the forming of the recessed portion includes using optical energy supplied by a laser to ablate the conductive contact to obtain the first thickness at the thin region.

4. The method of claim 3, wherein intensity, wavelength and duration of the optical energy supplied by the laser are controlled during the forming of the recessed portion.

5. The method of claim 1, wherein the first thickness is ninety percent of the second thickness.

6. The method of claim 1, wherein the first thickness is fifty percent of the second thickness.

7. The method of claim 1 further comprising:

attaching a packaging assembly at the rear surface of the semiconductor element to define a cavity aligned with the light detector in a direction normal to the rear surface.

8. The method of claim 1 further comprising:

before the forming of the recessed portion, attaching a first dielectric layer at the rear surface of the semiconductor element.

9. The method of claim 8, wherein before the forming of the recessed portion, the first dielectric layer is attached to the rear surface of the semiconductor element and then a glass layer which is part of a packaging assembly is attached to the first dielectric layer, such that the packaging assembly defines a cavity aligned with the light detector in a direction normal to the rear surface.

10. The method of claim 8, wherein before the forming of the recessed portion, the first dielectric layer is attached to a glass layer which is part of a packaging assembly and then the first dielectric layer is attached to the rear surface of the semiconductor element, such that the packaging assembly defines a cavity aligned with the light detector in a direction normal to the rear surface.

11. The method of claim 8, wherein a second dielectric layer having a thickness of about 1 to 5 microns is disposed on the rear surface of the semiconductor element and the first dielectric layer is attached to the second dielectric layer.

12. The method of claim 1, wherein the semiconductor element is attached to the packaging layer by a layer including adhesive material.

13. The method of claim 1, wherein, before forming the recessed portion, removing a portion of the packaging layer so the packaging layer has at least a predetermined thickness.

14. The method of claim 13, wherein the packaging layer includes silicon and the step of removing the portion of the packaging layer includes at least one of grinding and etching.

15. The method of claim 2, wherein the semiconductor element has a thickness of about 3 to 5 microns.