Staggered column superjunction

• US 8,900,949 B2
• Filed: 05/22/2013
• Issued: 12/02/2014
• Est. Priority Date: 10/30/2009
• Status: Active Grant

• Current Assignee: Alpha & Omega Semiconductor, Ltd.
• Original Assignee: Alpha & Omega Semiconductor, Ltd.
• Inventors: Guan, Lingpeng, Bobde, Madhur, Bhalla, Anup, Yilmaz, Hamza
• Primary Examiner(s): Vu, David
• Assistant Examiner(s): Han, Jonathan
• Application Number:
  US13/900,162
• Publication Number:
  US 20130260522A1
• Time in Patent Office: 559 Days
• Field of Search: 257/329, 257/341, 257/335, 438/268, 438/270
• US Class Current: 438/268
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A staggered column superjunction semiconductor device may include a cell region having one or more device cells. One or more device cells in the cell region include a semiconductor substrate configured to act as a drain and a semiconductor layer formed on the substrate. A first doped column may be formed in the semiconductor layer to a first depth and a second doped column may be formed in the semiconductor layer to a second depth. The first depth is greater than the second depth. The first and second columns are doped with dopants of a same second conductivity type and extend along a portion of a thickness of the semiconductor layer and are separated from each by a portion of the semiconductor layer.

Claims

1. A method of manufacturing a staggered column vertical superjunction semiconductor device comprising:

a) applying a first mask to a surface of a first semiconductor layer of a first conductivity type, wherein the first mask is patterned with openings positioned at locations where first columns are to be located and no openings at locations where second columns are to be located, wherein the first and second columns alternate with each other in a row;

b) implanting dopants having a second conductivity type into the first semiconductor layer through the openings of the first mask to form first implanted regions at the locations where the first columns are to be located without forming the first implanted regions at the locations where the second columns are to be located;

c) growing a second semiconductor layer of the first conductivity type on top of the first semiconductor layer;

d) applying a second mask on a surface of the second semiconductor layer, wherein the second mask is patterned with openings positioned at both the locations where the first columns are to be located and the locations where the second columns are to be located;

e) implanting dopants having the second conductivity type into the second semiconductor layer through the openings of the second mask to form second implanted regions at both the locations where the first columns are to be located and the locations where the second columns are to be located; and

f) repeating steps c) through e) one or more times to form the first and second columns of the second conductivity type in a cumulative semiconductor layer of the first conductivity type, whereby the cumulative semiconductor layer comprises the first semiconductor layer and a plurality of subsequent second semiconductor layers grown on top of it, and wherein at least some of the first columns are located in an active cell region.

2. The method of claim 1 wherein the first and second columns are substantially horizontally charge balanced with adjacent regions of the cumulative semiconductor layer.

3. The method of claim 1 wherein steps c) through e) are repeated from 3 to 5 times.

4. The method of claim 1 wherein steps c) through e) are repeated 4 times.

5. The method of claim 1 wherein the first conductivity type is N-type.

6. The method of claim 1 wherein the first conductivity type is P-type.

7. The method of claim 1 wherein a semiconductor substrate is located under the first semiconductor layer, and wherein the method further comprises providing a buffer layer located in a space between the semiconductor substrate and the first implanted regions.

8. The method of claim 1 wherein the first mask is patterned with openings positioned at locations corresponding to a first column and no openings at locations corresponding to a second column in an active cell area of the first semiconductor layer.

9. The method of claim 1 wherein the masks are patterned such that only the first columns are formed in a termination area of the cumulative semiconductor layer.

10. The method of claim 1 wherein steps c) through e) are repeated a plurality of times.