Trench power MOSFET structure with high cell density and fabrication method thereof

• US 8,900,950 B2
• Filed: 03/20/2012
• Issued: 12/02/2014
• Est. Priority Date: 04/11/2011
• Status: Active Grant

• Current Assignee: Super Group Semiconductor Co., Ltd.
• Original Assignee: Great Power Semiconductor Corp.
• Inventors: Hsu, Hsiu-Wen
• Primary Examiner(s): Such, Matthew W
• Assistant Examiner(s): CARPENTER, ROBERT K
• Application Number:
  US13/425,365
• Publication Number:
  US 20120256258A1
• Time in Patent Office: 987 Days
• Field of Search: None
• US Class Current: 438/270
• CPC Class Codes: H01L 29/456 on silicon
• CPC Class Codes: H01L 29/4933 with a silicide layer contacting the silicon layer, e.g. Polycide gate with a barrier layer between the silicide and silicon layers H01L29/4941
• CPC Class Codes: H01L 29/66719 With a step of forming an insulating sidewall spacer
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A fabrication method of a high cell density trench power MOSFET structure is provided. Form at least a gate trench in a silicon substrate and a gate dielectric layer on the silicon substrate. Form a gate polysilicon structure in the gate trench and cover by a passivation layer. Form a first-conductive-type body region in the silicon substrate and implant impurities with a second conductive type thereof to form a source doped region. Expose the gate polysilicon structure and the source doped region. Form a dielectric spacer having a predetermined thickness on a sidewall of the gate trench. Deposit metal on the gate polysilicon structure and the source doped region. A first and a second self-aligned silicide layer are respectively formed on the gate polysilicon structure and the source doped region. The dielectric spacer forms an appropriate distance between the first and the second self-aligned silicide layer.

Claims

1. A fabrication method of a trench power MOSFET structure with a cell density comprising the steps of:

forming at least a gate trench in a silicon substrate;

forming a gate dielectric layer lining exposed surfaces of the silicon substrate;

forming a gate polysilicon structure in the gate trench;

forming a passivation layer in the gate trench to cover the gate polysilicon structure;

forming a diffusion barrier layer on the passivation layer and on the surfaces of the silicon substrate after the step of forming the passivation layer in the gate trench, wherein a thickness of the diffusion barrier layer is in the range of 200-300 Å

;

forming a body region having a first conductive type in the silicon substrate;

forming a source doped region by implanting impurities of a second conductive type into the body region;

removing a portion of the gate dielectric layer and the passivation layer so as to expose the gate polysilicon structure and the source doped region;

forming a dielectric spacer with a predetermined thickness on a sidewall of the gate trench;

depositing a metal layer on the exposed surfaces of the gate polysilicon structure and the source doped region;

forming a first self-aligned silicide layer on the gate polysilicon structure and a second self-aligned silicide layer on the source doped region by using a thermal process;

forming a dielectric structure in the gate trench to shield the first self-aligned silicide layer; and

forming a source metal layer on the dielectric structure and the second self-aligned silicide layer.

2. The fabrication method of the trench power MOSFET structure with a cell density of claim 1, wherein after the step of implanting the impurities of the second conductive type into the body region, further comprises a step of applying a thermal drive-in process to the source doped region.

3. The fabrication method of the trench power MOSFET structure with a cell density of claim 1, wherein a vertical distance between an upper surface of the first self-aligned silicide layer and an upper surface of the second self-aligned silicide layer is larger than half depth of the source doped region.

4. The fabrication method of the trench power MOSFET structure with a cell density of claim 1, wherein the gate dielectric layer, the passivation layer, the dielectric spacer, and the dielectric structure are composed of an identical material.

5. The fabrication method of the trench power MOSFET structure with a cell density of claim 1, wherein the step of removing a portion of the gate dielectric layer and the passivation layer to expose the gate polysilicon structure and the source doped region comprises:

removing a portion of the gate dielectric layer to expose the sidewall of the gate trench and the silicon substrate prior to the step of forming the passivation layer in the gate trench.