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Trench power MOSFET structure with high cell density and fabrication method thereof

  • US 8,900,950 B2
  • Filed: 03/20/2012
  • Issued: 12/02/2014
  • Est. Priority Date: 04/11/2011
  • Status: Active Grant
First Claim
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1. A fabrication method of a trench power MOSFET structure with a cell density comprising the steps of:

  • forming at least a gate trench in a silicon substrate;

    forming a gate dielectric layer lining exposed surfaces of the silicon substrate;

    forming a gate polysilicon structure in the gate trench;

    forming a passivation layer in the gate trench to cover the gate polysilicon structure;

    forming a diffusion barrier layer on the passivation layer and on the surfaces of the silicon substrate after the step of forming the passivation layer in the gate trench, wherein a thickness of the diffusion barrier layer is in the range of 200-300 Å

    ;

    forming a body region having a first conductive type in the silicon substrate;

    forming a source doped region by implanting impurities of a second conductive type into the body region;

    removing a portion of the gate dielectric layer and the passivation layer so as to expose the gate polysilicon structure and the source doped region;

    forming a dielectric spacer with a predetermined thickness on a sidewall of the gate trench;

    depositing a metal layer on the exposed surfaces of the gate polysilicon structure and the source doped region;

    forming a first self-aligned silicide layer on the gate polysilicon structure and a second self-aligned silicide layer on the source doped region by using a thermal process;

    forming a dielectric structure in the gate trench to shield the first self-aligned silicide layer; and

    forming a source metal layer on the dielectric structure and the second self-aligned silicide layer.

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