Alignment for backside illumination sensor

• US 8,900,966 B2
• Filed: 10/02/2013
• Issued: 12/02/2014
• Est. Priority Date: 12/06/2007
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Liu, Jen-Cheng, Yaung, Dun-Nian, Wuu, Shou-Gwo
• Primary Examiner(s): POTTER, ROY KARL
• Application Number:
  US14/044,716
• Publication Number:
  US 20140094016A1
• Time in Patent Office: 426 Days
• Field of Search: 438/401, 438/459, 257/E21.536, 257/E21.211
• US Class Current: 438/401
• CPC Class Codes: H01L 21/71 Manufacture of specific parts of devices defined in group H01L21/70 H01L21/0405, H01L21/0445 , H01L21/28, H01L21/44, H01L21/48 take precedence
• CPC Class Codes: H01L 2223/54426 for alignment
• CPC Class Codes: H01L 2223/54453 for use prior to dicing
• CPC Class Codes: H01L 2223/5446 Located in scribe lines
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

Provided is an apparatus that includes an integrated circuit located in a first region of a substrate having first and second opposing major surfaces and an alignment mark located in a second region of the substrate and extending through the substrate between the first and second surfaces.

Claims

1. A method comprising:

providing a substrate having a first region and second region, wherein the first region includes an integrated circuit;

forming a recess in the second region of the substrate;

forming a material within the recess in the second region of the substrate;

forming another material within the recess, the another material being different than the material within the recess; and

removing a portion of the substrate to expose a portion of the material, wherein the exposed material is an alignment mark.

2. The method of claim 1, wherein the material includes a conductive material and the another material includes a dielectric material.

3. The method of claim 1, further comprising coupling the substrate to another substrate prior to removing the portion of the substrate to expose the portion of the material.

4. The method of claim 1, further comprising forming another recess in the first region;

and

forming the material within the another recess.

5. The method of claim 4, wherein the recess extends a first depth within the substrate and the another recess extends a second depth that is different than the first depth.

6. The method of claim 1, further comprising forming another material over the second region of the substrate prior to forming the recess in the second region;

and

removing the another material over the second region of the substrate after forming the material within the recess in the second region of the substrate to expose another portion of the material within the recess.

19. The method of claim 1, wherein the material includes a dielectric material.

20. The method of claim 1, further comprising forming an interconnect structure formed over a first surface of the substrate;

and

forming a pixel array over a second surface of the substrate that is opposite the first surface.

7. A method comprising:

forming a first recess in a semiconductor substrate, the first recess extending to a first depth in the semiconductor substrate;

forming a second recess in the semiconductor substrate, the second recess extending to a second depth in the semiconductor substrate, the second depth is different than the first depth;

forming a material within the first and second recesses; and

removing a portion of the semiconductor substrate to expose a portion of the material within the first recess.

8. The method of claim 7, wherein the material includes a dielectric material.

9. The method of claim 7, wherein the semiconductor substrate has a front side and opposing back side,

wherein forming the first recess in the semiconductor substrate includes forming the first recess in the front side of the semiconductor substrate, and

wherein removing the portion of the semiconductor substrate to expose the portion of the material within the first recess includes removing the portion from the back side of the semiconductor substrate.

10. The method of claim 7, wherein removing the portion of the semiconductor substrate to expose the portion of the material within the first recess includes performing an etching process to remove the portion of the semiconductor substrate.

11. The method of claim 7, wherein removing the portion of the semiconductor substrate to expose the portion of the material within the first recess includes performing one of a chemical mechanical polishing process and a grinding process to remove the portion of the semiconductor substrate.

12. The method of claim 7, further comprising forming another material over the semiconductor substrate prior to forming the material within the first and second recesses;

and

removing the another material over the semiconductor substrate after forming the material within the first and second recesses to expose the material within the first and second recesses.

13. The method of claim 7, wherein the material in the first recessed forms an alignment mark and the material in the second recess forms a shallow trench isolation feature.

14. A method comprising:

providing a substrate having a first surface opposing a second surface and first and second regions extending between the first and second surfaces, wherein the first region includes an integrated circuit;

forming an alignment mark in the second region of the substrate, wherein the alignment mark is exposed through at least one of the first and second surfaces of the substrate;

forming an interconnect structure formed over the first surface of the substrate; and

forming a pixel array over the second surface of the substrate.

15. The method of claim 14, wherein forming the alignment mark in the second region of the substrate includes:

forming a recess through the first surface of the substrate;

forming a material within the recess; and

removing a portion of the substrate from the second surface of the substrate.

16. The method of claim 15, wherein the material is conductive.

17. The method of claim 15, further comprising forming another recess in the first region;

and

forming the material within the another recess, wherein the recess extends to a first depth within the substrate and the another recess extends to a second depth that is different than the first depth.

18. The method of claim 17, wherein a top surface of the material in the recess and a top surface of the material in the another recess are substantially coplanar.