Method for producing a protective structure

• US 8,900,994 B2
• Filed: 06/09/2011
• Issued: 12/02/2014
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jeng, Shin-Puu, Chiou, Wen-Chih, Tsai, Fang Wen, Tsai, Chen-Yu
• Primary Examiner(s): DANG, PHUC T
• Application Number:
  US13/157,137
• Publication Number:
  US 20120313247A1
• Time in Patent Office: 1,272 Days
• Field of Search: 438/612, 438/613, 438/667, 257/621, 257/E23.011, 257/763
• US Class Current: 438/667
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76831 in via holes or trenches, e.g. non-conductive sidewall liners
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76871 Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68372 used to support a device or wafer when forming electrical connections thereto when forming bonding pads H01L24/03; when forming bump connectors H01L24/11; when forming layer connectors H01L24/27
• CPC Class Codes: H01L 2224/03002 for supporting the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/0345 Physical vapour deposition [PVD], e.g. evaporation, or sputtering
• CPC Class Codes: H01L 2224/03452 Chemical vapour deposition [CVD], e.g. laser CVD
• CPC Class Codes: H01L 2224/03462 Electroplating
• CPC Class Codes: H01L 2224/0347 using a lift-off mask
• CPC Class Codes: H01L 2224/0391 Forming a passivation layer after forming the bonding area
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05008 Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body, e.g.
• CPC Class Codes: H01L 2224/05018 being a conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05023 the whole internal layer protruding from the surface
• CPC Class Codes: H01L 2224/05025 the internal layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05073 Single internal layer
• CPC Class Codes: H01L 2224/05144 : Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/05147 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05155 : Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/05166 : Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05548 : Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/05552 : in top view
• CPC Class Codes: H01L 2224/05559 : non conformal layer on a patterned surface
• CPC Class Codes: H01L 2224/05562 : On the entire exposed surface of the internal layer
• CPC Class Codes: H01L 2224/05568 : the whole external layer protruding from the surface
• CPC Class Codes: H01L 2224/05647 : Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13023 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/13025 : the bump connector being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/1411 : the bump connectors being bonded to at least one common bonding area
• CPC Class Codes: H01L 2224/14181 : On opposite sides of the body
• CPC Class Codes: H01L 2224/16113 : the whole bump connector protruding from the surface
• CPC Class Codes: H01L 2224/16145 : the bodies being stacked
• CPC Class Codes: H01L 2224/16225 : the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2225/06513 : Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 : Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 : Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 24/03 : Manufacturing methods
• CPC Class Codes: H01L 24/05 : of an individual bonding area
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]

Abstract

A system and method for manufacturing a through silicon via is disclosed. An embodiment comprises forming a through silicon via with a liner protruding from a substrate. A passivation layer is formed over the substrate and the through silicon via, and the passivation layer and liner are recessed from the sidewalls of the through silicon via. Conductive material may then be formed in contact with both the sidewalls and a top surface of the through silicon via.

Claims

1. A method comprising:

forming a through silicon via in a substrate, the through silicon via having sidewalls covered by a liner, wherein the through silicon via has a first diameter at a first end of the through silicon via and the first diameter at a second end of the through silicon via;

forming a passivation layer conformally over the substrate and over the liner, the passivation layer having a top surface that is closer to the substrate than a top surface of the through silicon via;

recessing the passivation layer and the liner to expose the sidewalls of the through silicon via, the passivation layer having two different thicknesses after recessing the passivation layer and the liner; and

forming a conductive material in contact with the sidewalls of the through silicon via.

2. The method of claim 1, wherein the recessing the passivation layer and the liner is performed in the same step.

3. The method of claim 1, wherein the recessing the passivation layer and the liner further comprises:

recessing the passivation layer; and

recessing the liner, wherein the recessing the liner is performed in a separate step from the recessing the passivation layer.

4. The method of claim 1, wherein the forming a conductive material further comprises forming a redistribution layer.

5. The method of claim 1, wherein the liner comprises a first material and the passivation layer comprises the first material.

6. The method of claim 5, wherein the first material is silicon nitride.

7. The method of claim 1, wherein the forming the conductive material further comprises forming a glue layer.

8. The method of claim 7, wherein the glue layer is titanium.

9. The method of claim 1, wherein the passivation layer comprises one of silicon nitride, silicon carbide, silicon oxynitride, silicon oxide, or polymer.

10. A method comprising:

forming a liner in an opening in a first side of a semiconductor substrate;

filling the opening with a first conductive material;

thinning a second side of the semiconductor substrate to expose the liner;

recessing the semiconductor substrate such that the first conductive material protrudes from the second side of the semiconductor substrate;

forming a passivation layer over the second side of the semiconductor substrate and the first conductive material, the passivation layer having a first portion adjacent to and in contact with the second side and a second portion over the first portion and extending along a sidewall of the first conductive material;

recessing the first portion of the passivation layer and the liner to expose a sidewall of the first conductive material, wherein after recessing the first portion of the passivation layer and the liner, the passivation layer has a first thickness and a second thickness different from the first thickness; and

forming a second conductive material in physical contact with the sidewall and a top surface of the first conductive material, wherein the forming the second conductive material further comprises forming a redistribution layer to electrically connect the first conductive material to a third conductive material, the third conductive material extending through the semiconductor substrate.

11. The method of claim 10, wherein the forming the second conductive material further comprises:

forming a glue layer; and

forming a seed layer.

12. The method of claim 10, wherein the forming the second conductive material further comprises forming a contact pad.

13. The method of claim 10, wherein the passivation layer comprises a first material and the liner comprises the first material.

14. The method of claim 10, wherein the forming the second conductive material further comprises forming a layer of titanium over the passivation layer, the liner, and the first conductive material.

15. A method comprising:

forming a through silicon via in a substrate, the through silicon via being lined by a liner and having a constant diameter along the length of the through silicon via;

recessing the substrate from the through silicon via and the liner;

depositing a passivation layer over the through silicon via and the liner, the passivation layer having a first region with a first thickness adjacent to the through silicon via and a second region with a second thickness different from the first thickness adjacent to the first region;

recessing the passivation layer from the through silicon via and the liner; and

recessing the liner from the through silicon via, wherein the recessing the liner from the through silicon via is performed in a different step than the recessing the passivation layer and wherein the step of recessing the liner recesses the liner less than the step of recessing the passivation layer recesses the passivation layer.

16. The method of claim 15, further comprising forming a conductive material in contact with a sidewall of the through silicon via.

17. The method of claim 16, wherein the conductive material is a redistribution layer.

18. The method of claim 17, wherein the forming the conductive material further comprises:

forming a glue layer in contact with the sidewall of the through silicon via;

forming a seed layer in contact with the glue layer; and

forming the redistribution layer in contact with the glue layer.

19. The method of claim 15, wherein the liner comprises silicon nitride.

20. The method of claim 19, wherein the passivation layer comprises one of silicon carbide, silicon oxynitride, silicon oxide, or polymer.