Semiconductor device

• US 8,901,557 B2
• Filed: 06/10/2013
• Issued: 12/02/2014
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei
• Primary Examiner(s): Dickey, Thomas L
• Assistant Examiner(s): Schoenholtz, Joseph
• Application Number:
  US13/914,156
• Publication Number:
  US 20130334523A1
• Time in Patent Office: 540 Days
• Field of Search: None
• US Class Current: 257/43
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/04886 by partitioning the display area of the touch-screen or the surface of the digitising tablet into independently controllable areas, e.g. virtual keyboards or menus
• CPC Class Codes: H01L 27/14612 involving a transistor
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/267 in different semiconductor regions , e.g. heterojunctions H01L29/263 takes precedence
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H01L 31/03762 including only elements of Group IV of the Periodic Table
• CPC Class Codes: H01L 31/103 the potential barrier being of the PN homojunction type
• CPC Class Codes: H10K 59/40 OLEDs integrated with touch screens
• CPC Class Codes: H10K 59/65 OLEDs integrated with inorganic image sensors

Abstract

High field-effect mobility is provided for a transistor including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a bottom-gate transistor including an oxide semiconductor layer, an oxide semiconductor layer functioning as a current path (channel) of the transistor is sandwiched between oxide semiconductor layers having lower carrier densities than the oxide semiconductor layer. In such a structure, the channel is formed away from the interface of the oxide semiconductor stacked layer with an insulating layer in contact with the oxide semiconductor stacked layer, i.e., a buried channel is formed.

Claims

1. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor stacked layer overlapping with the gate electrode layer with the gate insulating layer therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stacked layer,

wherein the oxide semiconductor stacked layer comprises;

a first oxide semiconductor layer in contact with the gate insulating layer;

a second oxide semiconductor layer containing an impurity imparting n-type conductivity on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer on and in contact with the second oxide semiconductor layer, and

wherein the first oxide semiconductor layer and the third oxide semiconductor layer are i-type oxide semiconductor layers.

2. The semiconductor device according to claim 1,

wherein a carrier density of the first oxide semiconductor layer and a carrier density of the third oxide semiconductor layer are lower than a carrier density of the second oxide semiconductor layer.

3. The semiconductor device according to claim 1,

wherein an end portion of the first oxide semiconductor layer, an end portion of the second oxide semiconductor layer, and an end portion of the third oxide semiconductor layer are substantially aligned with each other.

4. The semiconductor device according to claim 1,

wherein the third oxide semiconductor layer covers the first oxide semiconductor layer and the second oxide semiconductor layer.

5. The semiconductor device according to claim 1,

wherein the impurity imparting n-type conductivity is selected from the group of boron, nitrogen, and phosphorus.

6. The semiconductor device according to claim 1,

wherein the first oxide semiconductor layer comprises a material represented by M1_aM2_bM3_cO_x, where a is a real number greater than or equal to 0 and less than or equal to 2, b is a real number greater than 0 and less than or equal to 5, c is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number, M1 is In, M2 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M3 is Zn,

wherein the second oxide semiconductor layer comprises a material represented by M4_dM5_eM6_fO_x, wherein d is a real number greater than 0 and less than or equal to 5, e is a real number greater than or equal to 0 and less than or equal to 3, f is a real number greater than 0 and less than or equal to 5, and x is a given real number, M4 is In, M5 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M6 is Zn, and

wherein the third oxide semiconductor layer comprises a material represented by M7_gM8_hM9_iO_x, where g is a real number greater than or equal to 0 and less than or equal to 2, h is a real number greater than 0 and less than or equal to 5, i is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number, M7 is In, M8 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M9 is Zn.

7. The semiconductor device according to claim 1,

wherein each of the first to third oxide semiconductor layers includes at least one metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr.

8. A semiconductor device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor stacked layer overlapping with the gate electrode layer with the gate insulating layer therebetween; and

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stacked layer,

wherein the oxide semiconductor stacked layer comprises;

a first oxide semiconductor layer in contact with the gate insulating layer;

a second oxide semiconductor layer containing an impurity imparting n-type conductivity on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer on and in contact with the second oxide semiconductor layer,

wherein the first to third oxide semiconductor layers include a same metal element, and

wherein the first oxide semiconductor layer and the third oxide semiconductor layer are i-type oxide semiconductor layers.

9. The semiconductor device according to claim 8,

wherein a carrier density of the first oxide semiconductor layer and a carrier density of the third oxide semiconductor layer are lower than a carrier density of the second oxide semiconductor layer.

10. The semiconductor device according to claim 8,

wherein an end portion of the first oxide semiconductor layer, an end portion of the second oxide semiconductor layer, and an end portion of the third oxide semiconductor layer are substantially aligned with each other.

11. The semiconductor device according to claim 8,

wherein the third oxide semiconductor layer covers the first oxide semiconductor layer and the second oxide semiconductor layer.

12. A display device comprising:

a gate electrode layer;

a gate insulating layer over the gate electrode layer;

an oxide semiconductor stacked layer overlapping with the gate electrode layer with the gate insulating layer therebetween;

a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor stacked layer, and

a pixel electrode electrically connected to the drain electrode layer,

wherein the oxide semiconductor stacked layer comprises;

a first oxide semiconductor layer in contact with the gate insulating layer;

a second oxide semiconductor layer containing an impurity imparting n-type conductivity on and in contact with the first oxide semiconductor layer; and

a third oxide semiconductor layer on and in contact with the second oxide semiconductor layer, and

wherein the first oxide semiconductor layer and the third oxide semiconductor layer are i-type oxide semiconductor layers.

13. The display device according to claim 12,

wherein a carrier density of the first oxide semiconductor layer and a carrier density of the third oxide semiconductor layer are lower than a carrier density of the second oxide semiconductor layer.

14. The display device according to claim 12,

wherein an end portion of the first oxide semiconductor layer, an end portion of the second oxide semiconductor layer, and an end portion of the third oxide semiconductor layer are substantially aligned with each other.

15. The display device according to claim 12,

wherein the third oxide semiconductor layer covers the first oxide semiconductor layer and the second oxide semiconductor layer.

16. The display device according to claim 12,

wherein the impurity imparting n-type conductivity is selected from the group of boron, nitrogen, and phosphorus.

17. The display device according to claim 12,

wherein the first oxide semiconductor layer comprises a material represented by M1_aM2_bM3_cO_x, where a is a real number greater than or equal to 0 and less than or equal to 2, b is a real number greater than 0 and less than or equal to 5, c is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number, M1 is In, M2 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M3 is Zn,

wherein the second oxide semiconductor layer comprises a material represented by M4_dM5_eM6_fO_x, wherein d is a real number greater than 0 and less than or equal to 5, e is a real number greater than or equal to 0 and less than or equal to 3, f is a real number greater than 0 and less than or equal to 5, and x is a given real number, M4 is In, M5 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M6 is Zn, and

wherein the third oxide semiconductor layer comprises a material represented by M7_gM8_hM9_iO_x, where g is a real number greater than or equal to 0 and less than or equal to 2, h is a real number greater than 0 and less than or equal to 5, i is a real number greater than or equal to 0 and less than or equal to 5, and x is a given real number, M7 is In, M8 is a metal element selected from the group of Ga, Mg, Hf, Al, Sn, and Zr, and M9 is Zn.