×

High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

  • US 8,901,566 B2
  • Filed: 08/31/2007
  • Issued: 12/02/2014
  • Est. Priority Date: 10/20/2003
  • Status: Active Grant
First Claim
Patent Images

1. A semiconductor structure, comprising:

  • a p-type field-effect-transistor (pFET) channel formed in a substrate;

    a n-type field-effect-transistor (nFET) channel formed in the substrate;

    a first layer of material in source and drain regions of the pFET channel having a lattice constant different than a lattice constant of the substrate, wherein the first layer of material is unrelaxed SiGe; and

    a second layer of material in source and drain regions of the nFET channel having a lattice constant different than the lattice constant of the substrate,wherein;

    the first layer of material is unrelaxed SiGe doped with p-type doping; and

    the second layer of material is Si;

    C doped with n-type doping.

View all claims
  • 3 Assignments
Timeline View
Assignment View
    ×
    ×