High performance stress-enhanced MOSFETs using Si:C and SiGe epitaxial source/drain and method of manufacture

• US 8,901,566 B2
• Filed: 08/31/2007
• Issued: 12/02/2014
• Est. Priority Date: 10/20/2003
• Status: Active Grant

• Current Assignee: Auriga Innovations, Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: International Business Machines Corporation
• Inventors: Chen, Huajie, Chidambarrao, Dureseti, Dokumaci, Omer H.
• Primary Examiner(s): MITCHELL, JAMES M
• Application Number:
  US11/848,268
• Publication Number:
  US 20070296038A1
• Time in Patent Office: 2,650 Days
• Field of Search: 257/69, 257/204, 257/616
• US Class Current: 257/69
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823814 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/66628 recessing the gate by forming single crystalline semiconductor material at the source or drain location
• CPC Class Codes: H01L 29/66636 with source or drain recessed by etching or first recessed by etching and then refilled
• CPC Class Codes: H01L 29/7848 the means being located in the source/drain region, e.g. SiGe source and drain
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device and method of manufacturing a semiconductor device. The semiconductor device includes channels for a pFET and an nFET. A SiGe layer is selectively grown in the source and drain regions of the pFET channel and a Si:C layer is selectively grown in source and drain regions of the nFET channel. The SiGe and Si:C layer match a lattice network of the underlying Si layer to create a stress component. In one implementation, this causes a compressive component in the pFET channel and a tensile component in the nFET channel.

Claims

1. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel formed in a substrate;

a n-type field-effect-transistor (nFET) channel formed in the substrate;

a first layer of material in source and drain regions of the pFET channel having a lattice constant different than a lattice constant of the substrate, wherein the first layer of material is unrelaxed SiGe; and

a second layer of material in source and drain regions of the nFET channel having a lattice constant different than the lattice constant of the substrate,

wherein;

the first layer of material is unrelaxed SiGe doped with p-type doping; and

the second layer of material is Si;

C doped with n-type doping.

2. The structure of claim 1, wherein the first layer of material and the second layer of material create different types of stresses, respectively, in the pFET channel and the nFET channel.

3. The structure of claim 1, wherein:

the first layer of material is embedded in the substrate;

the first layer of material has a thickness of about 10 m to 100 nm;

the first layer of material extends above a gate oxide;

the first layer of material is raised above a surface of the device by about 50 nm;

the lattice constant of the first layer of material is larger than the lattice constant of the substrate;

the first layer of material has a lattice structure that matches a lattice structure of the substrate;

the second layer of material is embedded in the substrate;

the second layer of material has a thickness of about 10 nm to 100 nm;

the second layer of material is raised above a surface of the device by about 50 nm;

the second layer of material has greater than 0% to 4% C in ratio to Si;

the lattice constant of the second layer of material is smaller than the lattice constant of the substrate;

the second layer of material has a lattice structure that matches a lattice structure of the substrate;

the first layer of material is directly adjacent to the pFET channel; and

the second layer of material is directly adjacent to the nFET channel.

4. The structure of claim 3, wherein:

a sidewall of the first material is vertically aligned with a spacer that is adjacent and contacting a pFET stack over the pFET channel; and

a sidewall of the second material is vertically aligned with a spacer that is adjacent and contacting a nFET stack over the nFET channel.

5. The structure of claim 1, wherein:

the pFET channel, the nFET channel, the first layer of material, and the second layer of material are in a silicon-on-insulator (SOI) layer of the substrate; and

the first material and the second material each have a thickness of between about 10 to 100 nm.

6. The structure of claim 1, wherein the Si:

C is not relaxed.

7. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a silicon-on-insulator (SOI) layer of a substrate;

a pFET stack in the pFET channel and an nFET stack in the nFET channel;

a first layer of material at source/drain regions associated with the pFET stack, the first layer of material being on opposing sides of the pFET channel, the first layer of material having an intrinsic lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel, wherein a lattice structure of the first layer of material matches a lattice structure of the substrate; and

a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having an intrinsic lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel, wherein a lattice structure of the second layer of material matches a lattice structure of the substrate,

wherein;

the first layer of material is unrelaxed SiGe doped with p-type doping; and

the second layer of material is Si;

C doped with n-type doping.

8. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate;

a pFET stack in the pFET channel and an nFET stack in the nFET channel;

a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel, wherein the first layer of material is unrelaxed SiGe doped with p-type doping; and

a second layer of material used as a replacement material for source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel.

9. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel in a substrate;

a pFET stack in the pFET channel and an nFET stack in the nFET channel;

a first layer of material at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate to create a compressive state within the pFET channel, wherein the first layer of material is unrelaxed SiGe doped with p-type doping; and

a second layer of material at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate to create a tensile state at the nFET channel,

wherein the first layer of material and the second layer of material are each grown to a thickness about 10 to 100 nm, and

wherein the first layer of material and the second layer of material are embedded in the substrate.

10. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel arranged in a substrate;

a pFET stack arranged in the pFET channel and an nFET stack arranged in the nFET channel;

a first layer of material arranged at source/drain regions associated with the pFET stack, the first layer of material contacting and being laterally adjacent to the pFET channel, the first layer of material having a lattice constant different than a base lattice constant of the substrate, wherein the first layer of material is unrelaxed SiGe doped with p-type doping; and

a second layer of material arranged at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate.

11. The structure of claim 10, wherein the first layer of material and the second layer of material are each grown to a thickness about 10 to 100 nm.

12. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel arranged in a substrate;

a pFET stack arranged in the pFET channel and an nFET stack arranged in the nFET channel;

a first layer of material arranged at source/drain regions associated with the pFET stack, the first layer of material having a lattice constant different than a base lattice constant of the substrate, wherein the first layer of material is unrelaxed SiGe doped with p-type doping; and

a second layer of material arranged at the source/drain regions associated with the nFET stack, the second layer of material having a lattice constant different than the base lattice constant of the substrate,

wherein the first layer of material and the second layer of material are embedded.

13. A semiconductor structure, comprising:

a p-type field-effect-transistor (pFET) channel and a n-type field-effect-transistor (nFET) channel arranged in a silicon-on-insulator (SOI) layer of a substrate;

a pFET structure and an nFET structure arranged on the substrate and associated with the pFET channel and the nFET channel, respectively;

a first material with a lattice constant different than a base lattice constant of the substrate arranged in source and drain regions of the pFET structure to provide a compressive stress in the pFET channel;

a second material with a lattice constant different than the base lattice constant of the substrate arranged in source and drain regions of the nFET structure to provide a tensile stress in the nFET channel; and

wherein the first material is unrelaxed SiGe doped with p-type doping and the second material is Si;

C doped with n-type doping to form the source and drain regions of the nFET and pFET structures, respectively.

14. The structure of claim 13, wherein the first material and the second material are embedded in the substrate.

15. The structure of claim 13, wherein the first material and the second material are raised above a surface of the substrate.

16. The structure of claim 13, wherein the first material and the second material each have a thickness of between about 10 to 100 nm.

17. The structure of claim 13, wherein:

the first material is embedded in the substrate;

the first material has a thickness of about 10 nm to 100 nm;

the first material extends above a gate oxide;

the first material is raised above a surface of the device by about 50 nm;

a sidewall of the first material is vertically aligned with a spacer that is adjacent and contacting a pFET stack over the pFET channel;

the second material is embedded in the substrate;

the second material has a thickness of about 10 nm to 100 nm;

the second material is raised above a surface of the device by about 50 nm;

the second material has greater than 0% to 4% C in ratio to Si;

a sidewall of the second material is vertically aligned with a spacer that is adjacent and contacting a nFET stack over the nFET channel;

the first layer of material is directly adjacent to the pFET channel; and

the second layer of material is directly adjacent to the nFET channel.