Semiconductor device and structure for heat removal

• US 8,901,613 B2
• Filed: 03/06/2011
• Issued: 12/02/2014
• Est. Priority Date: 03/06/2011
• Status: Expired due to Fees

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak C., Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US13/041,405
• Publication Number:
  US 20120223436A1
• Time in Patent Office: 1,367 Days
• Field of Search: 257202-211, 257/347, 257/E29.12, 257/E29.246
• US Class Current: 257/202
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/14 Integrated circuits

Abstract

A semiconductor device comprising power distribution wires wherein; a portion of said wires have thermal connection to the semiconductor layer and said thermal connection designed to conduct heat but to not conduct electricity.

Claims

1. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal interconnection layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm,

wherein said second transistors are interconnected to form logic circuits, and

wherein said second layer comprises a thermally conductive shallow trench isolation (STI).

2. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal interconnection layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm, and

wherein said second transistors are interconnected to form logic circuits,

a second metal interconnection layer overlaying said second transistors; and

an isolation layer disposed between said second transistors and said second metal interconnection layer,

wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.

3. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm,

wherein said second transistors are interconnected to form at least one NAND gate, and

wherein said second layer comprises a thermally conductive shallow trench isolation (STI).

4. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm, and

wherein said second transistors are interconnected to form at least one NAND gate,

a second metal interconnection layer overlaying said second transistors; and

an isolation layer disposed between said second transistors and said second metal interconnection layer,

wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.

5. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm,

wherein said second transistors are interconnected to form at least one transmission gate, and

wherein said second layer comprises a thermally conductive shallow trench isolation (STI).

6. A device, comprising:

an integrated circuit chip, wherein said integrated circuit chip comprises;

a first layer comprising a plurality of first transistors;

a first metal layer comprising aluminum or copper and providing interconnection between said first transistors;

a second layer comprising second transistors comprising a mono-crystal channel;

wherein said second layer has a thickness of less than 200 nm, and

wherein said second transistors are interconnected to form at least one transmission gate,

a second metal interconnection layer overlaying said second transistors; and

an isolation layer disposed between said second transistors and said second metal interconnection layer,

wherein said isolation layer has a thermal conductivity of greater than 0.6 W/m-K.