Charge compensation semiconductor device

• US 8,901,642 B2
• Filed: 03/07/2012
• Issued: 12/02/2014
• Est. Priority Date: 03/07/2012
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Weber, Hans, Hirler, Franz
• Primary Examiner(s): Trinh, Michael
• Assistant Examiner(s): Hillman, Damian A
• Application Number:
  US13/414,037
• Publication Number:
  US 20130234239A1
• Time in Patent Office: 1,000 Days
• Field of Search: 257/329, 257/327, 257/335, 257/583
• US Class Current: 257/329
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/167 further characterised by the doping material H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/408 with an insulating layer with a particular dielectric or electrostatic property, e.g. with static charges or for controlling trapped charges or moving ions, or with a plate acting on the insulator potential or the insulator charges, e.g. for controlling charges effect or potential distribution in the insulating layer, or with a semi-insulating layer contacting directly the semiconductor surface
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

A semiconductor device includes a semiconductor body having a first surface defining a vertical direction and a source metallization arranged on the first surface. In a vertical cross-section the semiconductor body further includes: a drift region of a first conductivity type; at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization; a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region, and a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and includes at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer.

Claims

1. A semiconductor device, comprising a semiconductor body having a first surface defining a vertical direction, and a source metallization arranged on the first surface, in a vertical cross-section the semiconductor body further comprising:

a drift region of a first conductivity type;

at least two compensation regions of a second conductivity type each of which forms a pn-junction with the drift region and is in low resistive electric connection with the source metallization;

a drain region of the first conductivity type having a maximum doping concentration higher than a maximum doping concentration of the drift region; and

a third semiconductor layer of the first conductivity type arranged between the drift region and the drain region and comprising at least one of a floating field plate and a floating semiconductor region of the second conductivity type forming a pn-junction with the third semiconductor layer.

2. The semiconductor device of claim 1, further comprising a second semiconductor layer comprised of a semiconductor material of the first conductivity type, arranged between and adjoining the drift region and the third semiconductor layer and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material.

3. The semiconductor device of claim 1, wherein a body region of the second conductivity type which adjoins the drift region is arranged between the first surface and each of the at least two compensation regions.

4. The semiconductor device of claim 1, further comprising a drain metallization in low resistive contact with the drain region, wherein the drift region is substantially depletable at a reverse voltage applied between the source metallization and the drain metallization that is lower than a rated breakdown voltage of the semiconductor device.

5. The semiconductor device of claim 1, wherein at least one of a sidewall of the floating field plate and a bottom wall of the floating field plate are insulated from the third semiconductor layer by a dielectric region to form a charge trap.

6. The semiconductor device of claim 5, wherein the dielectric region is, in a vertical cross-section, substantially U-shaped or V-shaped.

7. The semiconductor device of claim 1, wherein the floating field plate comprises at least one charge generating center.

8. The semiconductor device of claim 1, wherein the floating field plate comprises at least one of a cavity, a polycrystalline semiconductor material, an amorphous semiconductor material, a semiconductor material comprising lattice defects, a semiconductor material impurities forming deep traps, a silicide and a metal.

9. The semiconductor device of claim 1, wherein the floating field plate is arranged below the floating semiconductor region.

10. The semiconductor device of claim 1, wherein the floating field plate is spaced apart from the floating semiconductor region.

11. The semiconductor device of claim 1, wherein the at least two compensation regions extend, in the vertical direction, substantially along the drift region.

12. The semiconductor device of claim 1, wherein each of the at least two compensation regions is, in the vertical cross-section, formed as one of a substantially vertically orientated pillar and a substantially vertically orientated strip-type parallelepiped.

13. The semiconductor device of claim 1, wherein the floating semiconductor region is, in the vertical cross-section, formed as one of a substantially vertically orientated pillar and a substantially vertically orientated strip-type parallelepiped.

14. The semiconductor device of claim 1, wherein the third semiconductor layer is arranged below the drift region.

15. The semiconductor device of claim 1, wherein the third semiconductor layer comprises at least two spaced apart floating semiconductor regions arranged vertically below each other.

22. The semiconductor device of claim 1, wherein the floating semiconductor region is higher doped than the at least two compensation regions.

16. A semiconductor device, comprising a semiconductor body comprising:

a first surface defining a vertical direction;

a first semiconductor layer extending to the first surface and comprising a pn-compensation-structure;

a second semiconductor layer adjoining the first semiconductor layer, being comprised of a semiconductor material of a first conductivity type, and having a doping charge per horizontal area lower than a breakdown charge per area of the semiconductor material; and

a third semiconductor layer of the first conductivity type adjoining the second semiconductor layer and comprising at least one of a self-charging charge trap, a floating field plate and a semiconductor region of a second conductivity type forming a pn-junction with the third semiconductor layer.

17. The semiconductor device of claim 16, wherein the first semiconductor layer is of the first conductivity type and comprises at least two compensation regions of a second conductivity type, each of the at least two compensation regions forming a pn-junction with a first portion of the first semiconductor layer, the first portion of the first semiconductor layer being arranged between the at least two compensation regions and forming the pn-compensation-structure with the at least two compensation regions.

18. The semiconductor device of claim 17, further comprising a source metallization arranged on the first surface in low resistive contact with the at least two compensation regions, a drain region of the first conductivity type adjoining the third semiconductor layer and having a maximum doping concentration higher than a maximum doping concentration of the third semiconductor layer, and a drain metallization in low resistive contact with the drain region , wherein the first portion of the first semiconductor layer is substantially depletable at a reverse voltage between the source metallization and the drain metallization lower than a rated breakdown voltage of the semiconductor device.

19. The semiconductor device of claim 16, wherein the semiconductor region is a floating semiconductor region.

20. A semiconductor device, comprising a semiconductor body having a first surface defining a vertical direction, and a first metallization arranged on the first surface, the semiconductor body further comprising in a vertical cross-section:

a first semiconductor layer extending to the first surface and comprising a pn-compensation-structure connected to the first metallization; and

a third semiconductor layer of the first conductivity type arranged below the first semiconductor layer and comprising at least one of a floating field plate and a semiconductor region of a second conductivity type forming a closed pn-junction within the third semiconductor layer.

21. The semiconductor device of claim 20, wherein the first semiconductor layer is of the first conductivity type and comprises at least two compensation regions of a second conductivity type in low resistive electric connection with the first metallization, each of the at least two compensation regions forming a pn-junction with a first portion of the first semiconductor layer, the first portion of the first semiconductor layer being arranged between the at least two compensation regions and forming the pn-compensation-structure with the at least two compensation regions.