Power semiconductor device

• US 8,901,651 B2
• Filed: 11/07/2013
• Issued: 12/02/2014
• Est. Priority Date: 12/12/2012
• Status: Active Grant

• Current Assignee: KEC Corporation (PCA Corp.)
• Original Assignee: KEC Corporation (PCA Corp.)
• Inventors: Kim, Tae Wan
• Primary Examiner(s): Rodela, Eduardo A
• Application Number:
  US14/074,359
• Publication Number:
  US 20140159152A1
• Time in Patent Office: 390 Days
• Field of Search: 257/288, 257/328, 257/329, 257/330, 257/331, 257/335, 257/339, 257/355, 257/393, 257/487, 257/494, 257/495, 257/E29.027, 257/E29.066, 257/E29.127
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402

Abstract

A power semiconductor device is provided, which can prevent an electric field from concentrating on a diode region, and can improve a breakdown voltage by creating an impurity concentration gradient in the diode region to increase from a termination region to an active cell region to cause reverse current to be distributed to the active cell region.

Claims

1. A power semiconductor device having an active cell region, a diode region formed outside the active cell region and a termination region formed outside the diode region, the power semiconductor device comprising:

a semiconductor layer of a first conductivity type and a plurality of columns of a second conductivity type, formed in the active cell region, the diode region and the termination region, the plurality of second conductivity type columns spaced apart from each other to have a predetermined depth on the first conductivity type semiconductor;

a first well region of second conductivity type, formed in the diode region to have a predetermined depth on the first conductivity type semiconductor layer and the plurality of second conductivity type columns;

a second well region of second conductivity type, formed at a side adjacent to the active cell region to have a predetermined depth on the second conductivity type first well region; and

a third well region of second conductivity type, formed to have a predetermined depth on locations of the second conductivity type columns in the diode region, the locations corresponding to the second conductivity type columns adjacent to the termination region,

wherein the second conductivity type first well region has an impurity concentration lower than the second conductivity type second well region and higher than the second conductivity type third well region.

2. The power semiconductor device of claim 1, wherein the third well region of second conductivity type is further formed in the termination region to have a predetermined depth on locations corresponding to the plurality of second conductivity type columns.

3. The power semiconductor device of claim 2, further comprising an insulation layer formed in the diode region to cover top portions of the second conductivity type first well region, the second conductivity type second well region and the second conductivity type third well region.

4. The power semiconductor device of claim 3, wherein the insulation layer is further formed in the termination region to cover top portions of the second conductivity type third well region and the first conductivity type semiconductor layer.

5. The power semiconductor device of claim 3, wherein the insulation layer is an oxide layer.

6. The power semiconductor device of claim 1, wherein the second conductivity type first well region and the second conductivity type third well region in the diode region are brought into contact with each other.

7. The power semiconductor device of claim 1, wherein the second conductivity type third well region has a lower impurity concentration than the plurality of second conductivity type columns.

8. The power semiconductor device of claim 1, further comprising a substrate of first conductivity type, formed under the first conductivity type semiconductor layer.

9. The power semiconductor device of claim 1, wherein the first well region of second conductivity type is further formed in the active cell region to have a predetermined depth on the second conductivity type columns.

10. The power semiconductor device of claim 9, further comprising a source region of first conductivity type formed in the active cell region to have a predetermined depth on the second conductivity type first well region.

11. The power semiconductor device of claim 10, further comprising in the active cell region a gate electrode formed on the second conductivity type first well region and the first conductivity type source region.

12. The power semiconductor device of claim 10, wherein the second conductivity type first well region in the active cell region is brought into contact with the top surface of the second conductivity type columns.

13. The power semiconductor device of claim 9, wherein the second conductivity type first well region in the active cell region is brought into contact with the top surface of the second conductivity type columns.

14. The power semiconductor device of claim 1, further comprising an insulation layer formed in the diode region to cover top portions of the second conductivity type first well region, the second conductivity type second well region and the second conductivity type third well region.

15. The power semiconductor device of claim 14, wherein the insulation layer is further formed in the termination region to cover top portions of the second conductivity type third well region and the first conductivity type semiconductor layer.

16. The power semiconductor device of claim 1, wherein the first conductivity type is a conductivity type of a semiconductor region doped with an n type impurity, and the second conductivity type is a conductivity type of a semiconductor region doped with a p type impurity.

17. A power semiconductor device having an active cell region, a diode region formed outside the active cell region and a termination region formed outside the diode region, the power semiconductor device comprising:

a semiconductor layer of a first conductivity type and a plurality of columns of a second conductivity type, formed in the active cell region, the diode region and the termination region, the plurality of second conductivity type columns spaced apart from each other to have a predetermined depth on the first conductivity type semiconductor;

a first well region of second conductivity type, formed in the diode region to have a predetermined depth on the first conductivity type semiconductor layer and the plurality of second conductivity type columns;

a second well region of second conductivity type, formed at a side adjacent to the active cell region to have a predetermined depth on the second conductivity type first well region; and

a third well region of second conductivity type, formed to have a predetermined depth on locations of the second conductivity type columns in the diode region, the locations corresponding to the second conductivity type columns adjacent to the termination region,

wherein the third well region of second conductivity type is further formed in the termination region to have a predetermined depth on locations corresponding to the plurality of second conductivity type columns.

18. The power semiconductor device of claim 17, further comprising an insulation layer formed in the diode region to cover top portions of the second conductivity type first well region, the second conductivity type second well region and the second conductivity type third well region.

19. The power semiconductor device of claim 18, wherein the insulation layer is further formed in the termination region to cover top portions of the second conductivity type third well region and the first conductivity type semiconductor layer.

20. The power semiconductor device of claim 17, wherein the second conductivity type first well region and the second conductivity type third well region in the diode region are brought into contact with each other.