Semiconductor structures

• US 8,901,700 B2
• Filed: 12/13/2013
• Issued: 12/02/2014
• Est. Priority Date: 05/05/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Parekh, Kunal R., Zahurak, John K.
• Primary Examiner(s): TOBERGTE, NICHOLAS J
• Application Number:
  US14/105,595
• Publication Number:
  US 20140097499A1
• Time in Patent Office: 354 Days
• Field of Search: 257/244, 257/329, 257/506, 438/424, 438/427
• US Class Current: 257/506
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H10B 12/00 Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/053 the transistor being at least partially in a trench in the substrate vertical transistor in combination with a capacitor formed in a substrate trench H10B12/0383
• CPC Class Codes: H10B 12/488 Word lines

Abstract

Methods of pitch doubling of asymmetric features and semiconductor structures including the same are disclosed. In one embodiment, a single photolithography mask may be used to pitch double three features, for example, of a DRAM array. In one embodiment, two wordlines and a grounded gate over field may be pitch doubled. Semiconductor structures including such features are also disclosed.

Claims

1. A semiconductor structure comprising:

a plurality of semiconductor pillars in a substrate; and

a plurality of trenches isolating each pillar of the plurality of pillars, wherein the plurality of trenches and the plurality of pillars have equal width of less than 44 nm.

2. The semiconductor structure of claim 1, wherein the trenches comprise insulative material therein.

3. The semiconductor structure of claim 2, wherein the insulative material fills the trenches.

4. A semiconductor structure comprising a plurality of active areas separated by isolation regions, the plurality of active areas including FinFET trenches therein respectively having a width of less than a minimum feature size, a transistor gate being within individual of the FinFET trenches, the width of the plurality of active areas laterally outward of the transistor gates being less than the minimum feature size.

5. The semiconductor structure of claim 4, wherein the width of the isolation regions is less than the minimum feature size.

6. The semiconductor structure of claim 4, wherein the isolation regions comprise conductive lines.

7. The semiconductor structure of claim 4, wherein the isolation regions comprise dielectric material.

8. The semiconductor structure of claim 7, wherein the dielectric material comprises oxide.

9. A semiconductor structure comprising:

a plurality of active areas separated by isolation regions, the plurality of active areas including FinFET trenches therein respectively having a width of less than a minimum feature size;

conductive gate material within the FinFET trenches; and

a plurality of conductive lines elevationally outward of the plurality of active areas and FinFET trenches, some of the conductive lines connecting with the conductive gate material within the FinFET trenches.

10. The semiconductor structure of claim 9, wherein the conductive lines have widths of less than the minimum feature size.

11. The semiconductor structure of claim 9, wherein the conductive lines run parallel the FinFET trenches.

12. A semiconductor structure comprising a plurality of active areas separated by isolation regions, the plurality of active areas including FinFET trenches therein respectively having a width of less than a minimum feature size, conductive gate material within the FinFET trenches;

and

a plurality of conductive lines elevationally outward of the plurality of active areas and FinFET trenches, some of the conductive lines connecting with the conductive gate material within the FinFET trenches, another some of the conductive lines not connecting with the conductive gate material within the FinFET trenches.

13. The semiconductor structure of claim 12, wherein the another some of the conductive lines have widths of less than the minimum feature size.

14. The semiconductor structure of claim 12, wherein the another some of the conductive lines comprise grounded gate lines.

15. The semiconductor structure of claim 14, wherein the grounded gate lines have widths of less than the minimum feature size.

16. A semiconductor structure comprising a plurality of active areas separated by isolation regions, the plurality of active areas including FinFET trenches therein respectively having a width of less than a minimum feature size, conductive gate material within the FinFET trenches;

and

a plurality of conductive lines elevationally outward of the plurality of active areas and FinFET trenches, some of the conductive lines connecting with the conductive gate material within the FinFET trenches, the some of the conductive lines comprising word lines, and further comprising another some of the conductive lines which comprise grounded gate lines, two of the word lines being received between two immediately adjacent of the grounded gate lines.

17. The semiconductor structure of claim 16, wherein the grounded gate lines have widths of less than the minimum feature size.

18. The semiconductor structure of claim 16, wherein the word lines have widths of less than the minimum feature size.

19. The semiconductor structure of claim 16, wherein the word lines have widths of less than the minimum feature size and the grounded gate lines have widths of less than the minimum feature size.