Reducing the effect of parasitic mismatch at amplifier inputs

• US 8,902,004 B2
• Filed: 09/27/2012
• Issued: 12/02/2014
• Est. Priority Date: 09/27/2012
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Quinn, Patrick J., Jennings, John K., Walsh, Darragh, Kelly, Padraig
• Primary Examiner(s): Pascal, Robert
• Assistant Examiner(s): NGUYEN, KHIEM D
• Application Number:
  US13/629,123
• Publication Number:
  US 20140085003A1
• Time in Patent Office: 796 Days
• Field of Search: 330/68, 330/253, 330/207.P
• US Class Current: 330/253
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 3/45 Differential amplifiers differential sense amplifiers G11C7/062
• CPC Class Codes: Y10T 29/49002 Electrical device making

Abstract

A circuit includes an amplifier including a differential input stage including a first input terminal and a second input terminal. The circuit further includes a differential input line coupled to the first input terminal and the second input terminal, and shielding at least partially encompassing the differential input line. The shielding is connected to a node of the differential input stage of the amplifier.

Claims

1. A circuit, comprising:

an amplifier comprising a differential input stage including a first input terminal and a second input terminal;

a differential input line coupled to the first input terminal and the second input terminal; and

shielding at least partially encompassing the differential input line;

wherein the shielding is connected to a node of the differential input stage of the amplifier;

the differential input stage comprises;

a first transistor having a source, a drain, and a gate;

a second transistor having a source, a drain, and a gate; and

wherein the source of the first transistor is connected to the source of the second transistor forming the node.

2. The circuit of claim 1, wherein the differential input stage includes an input differential metal-oxide semiconductor field-effect transistor (MOSFET) pair.

3. The circuit of claim 1, wherein the node is a common source node.

4. The circuit of claim 1, wherein:

the gate of the first transistor is connected to the first input terminal; and

the gate of the second transistor is connected to the second input terminal.

5. The circuit of claim 1, wherein the amplifier is part of a switched capacitor circuit.

6. The circuit of claim 1, wherein the amplifier is part of a data converter circuit.

7. The circuit of claim 6, wherein the shield is located on each side of the differential input line.

8. The circuit of claim 7, wherein the shielding is formed of at least two conductive elements.

9. The circuit of claim 1, wherein the differential input line and the shielding are substantially parallel.

10. The circuit of claim 9, wherein the differential input line and the shielding are substantially perpendicular to process layers of an integrated circuit manufacturing process used to implement the circuit.

11. The circuit of claim 1, wherein:

the first input terminal is connected to a first capacitor by a first input line of the differential input line; and

the second input terminal is connected to a second capacitor by a second input line of the differential input line.

12. A method, comprising:

providing an amplifier comprising a differential input stage including a first input terminal and a second input terminal;

connecting a differential input line to the first input terminal and the second input terminal;

forming shielding at least partially encompassing the differential input line; and

connecting the shielding to a node of the differential input stage of the amplifier

wherein the differential input stage comprises;

a first transistor having a source, a drain, and a gate; and

a second transistor having a source, a drain, and a gate;

wherein the source of the first transistor is connected to the source of the second transistor forming the node.

13. The method of claim 12, wherein the differential input stage includes an input differential metal-oxide semiconductor field-effect transistor (MOSFET) pair.

14. The method of claim 12, wherein the node is a common source node.

15. The method of claim 12, wherein:

the gate of the first transistor is coupled to the first input terminal; and

the gate of the second transistor is coupled to the second input terminal.

16. The method of claim 12, wherein the differential input line and the shielding are substantially parallel.

17. The method of claim 16, wherein the differential input line and the shielding are substantially perpendicular to process layers of an integrated circuit manufacturing process used to implement the circuit.

18. The method of claim 12, wherein the shielding is formed of at least two conductive elements.