Display device

• US 8,902,145 B2
• Filed: 11/04/2011
• Issued: 12/02/2014
• Est. Priority Date: 09/29/2006
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Umezaki, Atsushi, Miyake, Hiroyuki
• Primary Examiner(s): Mengistu, Amare
• Assistant Examiner(s): XAVIER, ANTONIO J
• Application Number:
  US13/289,084
• Publication Number:
  US 20120049184A1
• Time in Patent Office: 1,124 Days
• Field of Search: None
• US Class Current: 345/92
• CPC Class Codes: G09G 2300/0809 Several active elements per pixel in active matrix panels
• CPC Class Codes: G09G 2310/0205 Simultaneous scanning of several lines in flat panels
• CPC Class Codes: G09G 2310/0248 Precharge or discharge of column electrodes before or after applying exact column voltages
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0289 Details of voltage level shifters arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/0291 Details of output amplifiers or buffers arranged for use in a driving circuit
• CPC Class Codes: G09G 2310/061 for resetting or blanking
• CPC Class Codes: G09G 2320/0646 Modulation of illumination source brightness and image signal correlated to each other
• CPC Class Codes: G09G 2320/0666 for control of colour parameters, e.g. colour temperature
• CPC Class Codes: G09G 3/2092 Details of a display terminals using a flat panel, the details relating to the control arrangement of the display terminal and to the interfaces thereto suitable for both CRT and flat panel G09G5/003; specific for a CRT G09G1/165
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3677 suitable for active matrices only
• CPC Class Codes: G11C 19/28 using semiconductor elements G11C19/14, G11C19/36 take precedence
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/1222 with a particular composition, shape or crystalline structure of the active layer
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52

Abstract

To suppress fluctuation in the threshold voltage of a transistor, to reduce the number of connections of a display panel and a driver IC, to achieve reduction in power consumption of a display device, and to achieve increase in size and high definition of the display device. A gate electrode of a transistor which easily deteriorates is connected to a wiring to which a high potential is supplied through a first switching transistor and a wiring to which a low potential is supplied through a second switching transistor; a clock signal is input to a gate electrode of the first switching transistor; and an inverted clock signal is input to a gate electrode of the second switching transistor. Thus, the high potential and the low potential are alternately applied to the gate electrode of the transistor which easily deteriorates.

Claims

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,

wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein a gate of the eighth transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the second transistor is directly connected to one of a plurality of wirings,

wherein the other of the source and the drain of the fourth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the seventh transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the eighth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the first transistor is electrically connected to another one of the plurality of wirings,

wherein the other of the source and the drain of the fifth transistor is directly connected to an additional one of the plurality of wirings,

wherein a gate of the third transistor is electrically connected to the another one of the plurality of wirings,

wherein a clock signal is input to the gate of the second transistor, and

wherein the clock signal is input to the gate of the fourth transistor.

2. The semiconductor device according to claim 1, wherein the gate of the third transistor is directly connected to the another one of the plurality of wirings.

3. The semiconductor device according to claim 1, wherein the other of the source and the drain of the third transistor is electrically connected to the additional one of the plurality of wirings.

4. The semiconductor device according to claim 1, wherein the second transistor comprises a channel region comprising an oxide semiconductor.

5. The semiconductor device according to claim 4, wherein the oxide semiconductor comprises In and Zn.

6. The semiconductor device according to claim 5, wherein the oxide semiconductor comprises InGaZnO.

7. The semiconductor device according to claim 6, wherein the oxide semiconductor comprises a-InGaZnO.

8. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,

wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein a gate of the eighth transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the second transistor is directly connected to one of a plurality of wirings,

wherein the other of the source and the drain of the fourth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the seventh transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the eighth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the first transistor is electrically connected to another one of the plurality of wirings,

wherein a gate of the third transistor is electrically connected to the another one of the plurality of wirings,

wherein a first clock signal is input to the gate of the second transistor, and

wherein the first clock signal is input to the gate of the fourth transistor.

9. The semiconductor device according to claim 8, wherein the gate of the third transistor is directly connected to the another one of the plurality of wirings.

10. The semiconductor device according to claim 8, wherein a second clock signal is input to the other of the source and the drain of the fifth transistor.

11. The semiconductor device according to claim 8, wherein the second transistor comprises a channel region comprising an oxide semiconductor.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor comprises In and Zn.

13. The semiconductor device according to claim 12, wherein the oxide semiconductor comprises InGaZnO.

14. The semiconductor device according to claim 13, wherein the oxide semiconductor comprises a-InGaZnO.

15. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor;

a seventh transistor; and

an eighth transistor,

wherein one of a source and a drain of the first transistor is directly connected to one of a source and a drain of the second transistor,

wherein one of a source and a drain of the third transistor is directly connected to one of a source and a drain of the fourth transistor,

wherein a gate of the fourth transistor is directly connected to a gate of the second transistor,

wherein one of a source and a drain of the fifth transistor is directly connected to a gate of the first transistor,

wherein one of a source and a drain of the sixth transistor is directly connected to the gate of the first transistor,

wherein a gate of the sixth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein one of a source and a drain of the seventh transistor is directly connected to the gate of the first transistor,

wherein one of a source and a drain of the eighth transistor is directly connected to the one of the source and the drain of the third transistor,

wherein a gate of the eighth transistor is directly connected to the gate of the first transistor,

wherein the other of the source and the drain of the second transistor is directly connected to one of a plurality of wirings,

wherein the other of the source and the drain of the fourth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the sixth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the seventh transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the eighth transistor is directly connected to the one of the plurality of wirings,

wherein the other of the source and the drain of the first transistor is electrically connected to another one of the plurality of wirings, and

wherein the other of the source and the drain of the fifth transistor is directly connected to an additional one of the plurality of wirings.

16. The semiconductor device according to claim 15, wherein the second transistor comprises a channel region comprising an oxide semiconductor.

17. The semiconductor device according to claim 16, wherein the oxide semiconductor comprises In and Zn.

18. The semiconductor device according to claim 16, wherein the oxide semiconductor comprises InGaZnO.

19. The semiconductor device according to claim 16, wherein the oxide semiconductor comprises a-InGaZnO.