Resistive memory device and sensing margin trimming method thereof

• US 8,902,628 B2
• Filed: 05/31/2012
• Issued: 12/02/2014
• Est. Priority Date: 06/09/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Ha, Daewon, Lee, Jung Hyuk
• Primary Examiner(s): Nguyen, Tuan T
• Application Number:
  US13/485,163
• Publication Number:
  US 20120314478A1
• Time in Patent Office: 915 Days
• Field of Search: 365/148, 365/189.011, 365/225.7, 365/189.07, 365/185.2
• US Class Current: 365/148
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/003 Cell access
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2213/75 Array having a NAND structure comprising, for example, memory cells in series or memory elements in series, a memory element being a memory cell in parallel with an access transistor
• CPC Class Codes: G11C 8/10 Decoders

Abstract

A resistive memory device and a sensing margin trimming method are provided. The resistive memory device includes a memory cell array and a trimming circuit. The memory cell array has a plurality of resistive memory cells. The trimming circuit generates a trimming signal according to a characteristic distribution shift value of the resistive memory cells. With the inventive concept, although a characteristic distribution of memory cells is varied, an erroneous read operation is minimized or reduced by securing a sensing margin stably. Accordingly, a fabrication yield of the resistive memory device is bettered.

Claims

1. A resistive memory device comprising:

a memory cell array having a plurality of resistive memory cells; and

a trimming circuit configured to generate a trimming signal according to a characteristic distribution shift value of the resistive memory cells.

2. The resistive memory device of claim 1, wherein the characteristic distribution shift value is obtained based on a shift of a peak distribution value of a reset current for the resistive memory cells.

3. The resistive memory device of claim 1, further comprising a read circuit, wherein the trimming signal is applied to the read circuit.

4. The resistive memory device of claim 3, wherein the read circuit includes a sense amplifier, wherein the trimming signal is applied as a sensing reference value to the sense amplifier.

5. The resistive memory device of claim 3, wherein the read circuit includes a biasing part, wherein the trimming signal is applied as a bias value to the biasing part.

6. The resistive memory device of claim 1, further comprising a write circuit, wherein the trimming signal is applied to the write circuit.

7. The resistive memory device of claim 6, wherein at least one fuse connected with the write circuit is disconnected according to the trimming signal.

8. The resistive memory device of claim 1, wherein the resistive memory device includes a PRAM or an MRAM.

9. The resistive memory device of claim 1, wherein the characteristic distribution shift value is determined according to resistance values at set and reset tails of a resistance distribution of the resistive memory cells.

10. The resistive memory device of claim 9, wherein the trimming signal is determined to correspond to an intermediate value between the resistance values at the set and reset tails.

11. The resistive memory device of claim 1, wherein the characteristic distribution shift value is determined according to resistance values at set and reset peaks of a resistance distribution of the resistive memory cells.

12. The resistive memory device of claim 11, wherein the trimming signal is determined to correspond to an intermediate value between the resistance values of the set and reset peaks.

13. A read method of a resistive memory device which includes a plurality of resistive memory cells, the read method comprising:

generating a trimming signal corresponding to a characteristic distribution shift value of the resistive memory cells;

generating a read reference level according to the trimming signal; and

determining a data level of a sensing node according to the read reference level.

14. The read method of claim 13, wherein the characteristic distribution shift value is obtained based on a shift of a peak distribution value of a reset current for the resistive memory cells.

15. The read method of claim 13, wherein the characteristic distribution shift value is determined according to resistance values at a set tail of a resistance distribution of set memory cells of the resistive memory cells and resistance values at a reset tail of a resistance distribution of reset memory cells of the resistive memory cells.

16. A memory device comprising:

at least one memory cell;

a lead circuit configured to compare a cell voltage with a reference voltage and to output a result of the comparison; and

a trimming circuit configured to generate the reference signal, wherein a value of the reference signal shifts depending on a characteristic distribution shift value of the at least one memory cell.

17. The memory device of claim 16, wherein the characteristic distribution shift value is determined based on a shift of a peak distribution value of a reset current for the at least one memory cell.

18. The memory device of claim 16, wherein the characteristic distribution shift value is determined based on resistance values at set and reset tails or peaks of a resistance distribution for the at least one memory cell.

19. The memory device of claim 16, wherein trimming circuit includes a plurality of resistors, which are connected in series between a power supply voltage and a ground, and a plurality of switching elements that are respectively connected to the plurality of resistors.

20. The memory device of claim 16, wherein trimming circuit includes a plurality of resistors, which are connected in series between a power supply voltage and a ground, and a plurality of fuses that are respectively connected to the plurality of resistors.