Forward error correction decoder

• US 8,902,925 B2
• Filed: 05/01/2012
• Issued: 12/02/2014
• Est. Priority Date: 05/01/2012
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Kim, Seuk B., Wente, Douglas E.
• Primary Examiner(s): Vu, Huy D
• Assistant Examiner(s): CUNNINGHAM, KEVIN M
• Application Number:
  US13/461,466
• Publication Number:
  US 20130294459A1
• Time in Patent Office: 945 Days
• Field of Search: None
• US Class Current: 370/465
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

A method for determining an initial alignment for a frame of input data is provided. A frame for the input data is set, and the frame is synchronized. Specifically, a syndrome check of the frame is performed using a first predetermined number of bits, and a slip of a second predetermined number of bits is requested following the syndrome check. Evaluation of the syndrome check to determine whether the frame is aligned can then be performed in parallel with the slipping. The evaluation and slipping can then be repeated if the frame is misaligned. When the frame is aligned, a lock condition can be indicated, and the slip performed in parallel with the evaluation indicating that the frame is aligned can be deasserted. In addition, when the frame is aligned, error correction on the frame can be performed, and the error corrected frame can be formatted.

Claims

1. A method comprising:

receiving input data;

setting a frame for the input data;

synchronizing the frame by;

performing a syndrome check of the frame using a first predetermined number of bits;

requesting a slip of a second predetermined number of bits following the step of performing the syndrome check, wherein the requesting of the slip occurs irrespective of a result of the syndrome check;

evaluating the syndrome check in parallel with the step of requesting the slip to determine whether the frame is aligned;

repeating the steps of performing and evaluating if the frame is misaligned; and

when the frame is aligned, indicating a lock condition; and

when the frame is aligned, deasserting the slip performed in parallel with the evaluation indicating that the frame is aligned;

performing error correction on the frame that is aligned to generate an error corrected frame; and

formatting the error corrected frame.

2. The method of claim 1, wherein the method further comprises descrambling the frame following the step of setting.

3. The method of claim 2, wherein the step of formatting further comprises:

generating output data; and

generating a header that corresponds to the output data.

4. The method of claim 3, wherein the step of descrambling further comprises descrambling the frame with a pseudo-noise sequence.

5. The method of claim 4, wherein the step of receiving further comprises receiving the input data from a physical medium attachment (PMA) sublayer, and wherein the method further comprises outputting the output data and header to a physical coding (PCS) sublayer.

6. The method of claim 5, wherein the first predetermined number of bits is 32, and wherein the second predetermined number of bits is 1.

7. An apparatus comprising:

physical medium dependant (PMD) sublayer logic that is configured to communicate with a communications medium;

PMA sublayer logic that is coupled to the PMD logic;

PCS sublayer logic that is configured to communicate with an interface; and

forward error correction (FEC) sublayer logic having;

an encoder that is coupled to the PMA sublayer logic; and

a decoder having;

a framer that is coupled to the PMA sublayer logic so as to receive input data, wherein the framer is configured to set a frame for the input data;

a syndrome generator that is coupled to the framer, wherein the syndrome generator is configured to perform a syndrome check of the frame using a first predetermined number of bits, and wherein the syndrome generator is configured to request a slip of a second predetermined number of bits by the framer following the syndrome check, wherein the requesting of the slip occurs irrespective of a result of the syndrome check;

a lock state machine that is coupled to the syndrome generator and the framer, wherein the lock state machine is configured to evaluate the syndrome check in parallel with the slip to determine whether the frame is aligned, and wherein the lock state machine is configured to indicate a lock condition when the frame is aligned, and wherein the lock state machine is configured to request deassertion of the slip performed in parallel with the evaluation indicating that the frame is aligned;

an error correction circuit that is coupled to the lock state machine and the syndrome generator; and

a formatter that is coupled to the error correction circuit and the PCS sublayer logic.

8. The apparatus of claim 7, wherein the FEC sublayer logic further comprises a descrambling circuit that is coupled between the framer and the syndrome generator.

9. The apparatus of claim 8, wherein the descrambling circuit further comprises:

a pseudorandom number generator; and

a combiner that is coupled between the framer and the syndrome generator and that is coupled to the pseudorandom number generator.

10. The apparatus of claim 9, wherein the FEC sublayer logic further comprises a first-in-first-out (FIFO) memory coupled between the syndrome generator and the error correction circuit.

11. The apparatus of claim 10, wherein the formatter is a 64b/66b formatter.

12. The apparatus of claim 11, wherein the first predetermined number of bits is 32, and wherein the second predetermined number of bits is 1.

13. The apparatus of claim 12, wherein the pseudorandom number generator is configured to generate a pseudo-noise sequence that is 2112 bits in length.

14. An apparatus comprising:

a communications medium;

a plurality of network interfaces, wherein each network interface includes;

a media access control (MAC) circuit;

a media independent interface (MII) that is coupled to the MAC circuit; and

a physical transceiver (PHY) having;

PMD sublayer logic that is configured to communicate with a communications medium;

PMA sublayer logic that is coupled to the PMD logic;

PCS sublayer logic that is coupled to the MII; and

FEC sublayer logic having;

an encoder that is coupled to the PMA sublayer logic; and

a decoder having;

 

a framer that is coupled to the PMA sublayer logic so as to receive input data, wherein the framer is configured to set a frame for the input data;

 

a syndrome generator that is coupled to the framer, wherein the syndrome generator is configured to perform a syndrome check of the frame using a first predetermined number of bits, and wherein the syndrome generator is configured to request a slip of a second predetermined number of bits by the framer following the syndrome check, wherein the requesting of the slip occurs irrespective of a result of the syndrome check;

 

a lock state machine that is coupled to the syndrome generator and the framer, wherein the lock state machine is configured to evaluate the syndrome check in parallel with the slip to determine whether the frame is aligned, and wherein the lock state machine is configured to indicate a lock condition when the frame is aligned, and wherein the lock state machine is configured to request deassertion of the slip performed in parallel with the evaluation indicating that the frame is aligned;

 

an error correction circuit that is coupled to the lock state machine and the syndrome generator; and

 

a formatter that is coupled to the error correction circuit and the PCS sublayer logic.

15. The apparatus of claim 14, wherein the FEC sublayer logic further comprises a descrambling circuit that is coupled between the framer and the syndrome generator.

16. The apparatus of claim 15, wherein the descrambling circuit further comprises:

a pseudorandom number generator; and

a combiner that is coupled between the framer and the syndrome generator and that is coupled to the pseudorandom number generator.

17. The apparatus of claim 16, wherein the FEC sublayer logic further comprises a FIFO memory coupled between the syndrome generator and the error correction circuit.

18. The apparatus of claim 17, wherein the apparatus further comprises a plurality of hosts, wherein each host is coupled to at least one of the MAC circuits.

19. The apparatus of claim 18, wherein the formatter is a 64b/66b formatter.

20. The apparatus of claim 19, wherein the first predetermined number of bits is 32, and wherein the second predetermined number of bits is 1, and wherein the pseudorandom number generator is configured to generate a pseudo-noise sequence that is 2112 bits in length.