Apparatus and method for capturing serial input data

• US 8,904,046 B2
• Filed: 09/10/2010
• Issued: 12/02/2014
• Est. Priority Date: 12/06/2006
• Status: Active Grant

• Current Assignee: NovaChips Canada Inc. (NovaChips Co., Ltd.)
• Original Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Inventors: Pyeon, Hong Beom, Oh, HakJune
• Primary Examiner(s): Unelus, Ernest
• Assistant Examiner(s): TAYLOR, BROOKE JAZMOND
• Application Number:
  US12/879,543
• Publication Number:
  US 20100332685A1
• Time in Patent Office: 1,544 Days
• Field of Search: 710/5
• US Class Current: 710/5
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A serial input processing apparatus provides how to capture serial data without loss of a single bit while command interpretation is being performed in a command decoder at high frequency. Individual bytes of serial bits of a pre-defined sequence are latched and bit streams are temporarily stored with multiple clocks. The temporary store is conducted before transferring byte information to assigned address registers to register the address. The address registration and the data registration are performed by latching all bit streams of the serial input at the leading edges of clocks. While at a high frequency operation (e.g., 1 GHz or 1 ns cycle time), no additional registers are required for storing bit data during command interpretation with enough time margins between the command bit stream interpretation and next bit data stream.

Claims

1. An apparatus for processing a serial input (SI) including command, address and data in accordance with at least one pre-defined sequence and grouped as input bit streams representing the command, address and data and for accessing a memory for data processing, the apparatus comprising:

a temporary holding circuit for temporarily storing the address bit streams of the SI, wherein the temporary holding circuit comprises J temporary registers that are serially connected, so that one register forwards its stored bit stream to the next register;

an address register circuit for storing the address bit streams temporarily stored in the temporary holding circuit to access the memory, wherein the address register circuit comprises J address registers for storing the address transferred from the J temporary registers, J being an integer greater than one;

an interpreting circuit for interpreting the command of the SI, independently of the address bit streams being temporarily held by the temporary holding circuit; and

a determination circuit for determining which of the temporarily stored address bit streams corresponds to row address information or column address information, in response to the interpreted command.

2. The apparatus of claim 1, wherein the interpreting circuit comprises:

a storing circuit for storing the command; and

a decoding circuit for decoding the stored command to determine an operation control mode of the command.

3. The apparatus of claim 2, further comprising:

a clock generation circuit for generating operation clocks in response to the operation control mode.

4. The apparatus of claim 3, further comprising:

a path circuit for establishing a transfer path of the temporarily stored address bit streams from the temporary holding circuit to the address register circuit in response to the operation control modes.

5. The apparatus of claim 4, wherein the path circuit comprises:

a switch circuit for selecting address transfer paths between the J temporary registers and the J address registers, in accordance with address switching information of the operation control mode.

6. The apparatus of claim 4, wherein the path circuit comprises:

a pre-defined transfer path for transferring the temporarily stored addresses from the J temporary registers to the J address registers therethrough.

13. The apparatus of claim 1, wherein the path circuit comprises:

a pre-defined transfer path for transferring the temporarily stored address from the J temporary registers to the corresponding one of the J address registers therethrough.

7. An apparatus including a plurality of devices in a serial interconnection configuration, each of the devices having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, each of the devices having an apparatus for capturing serial data, at least one of the devices comprising:

a serial input circuit for receiving serial input (SI) of command, address and data according to at least one pre-defined sequence and grouped as bytes in input bit streams representing the command, the address and the data;

a temporary holding circuit for temporarily storing the address bit streams of the received SI wherein the temporary holding circuit comprises J temporary registers that are serially connected, so that one register forwards its stored bit stream to the next register;

an address register circuit for storing the address bit streams temporarily stored in the temporary holding circuit to access the memory, wherein the address register circuit comprises J address registers for storing the address transferred from the J temporary registers, J being an integer greater than one;

an interpreting circuit for interpreting the command of the SI, independently of the command being held by the temporary holding circuit; and

a determination circuit for determining which of the temporarily stored address bit streams corresponds to row address information or column address information, in response to the interpreted command.

8. The apparatus of claim 7, wherein the interpreting circuit comprises:

a control determination circuit for decoding the stored command and sorting the decoded commands to determine an operation control mode of the command.

9. The apparatus of claim 7, wherein the J address registers comprise:

K registers for storing column address of the address transferred from the J temporary registers, K being an integer greater than one; and

(J−

K) registers for storing row address of the address transferred from the J temporary registers.

10. The apparatus of claim 9, wherein J is five and K is two.

11. The apparatus of claim 9, wherein the device further comprises:

a path circuit for establishing a transfer path of temporarily stored address from the temporary holding circuit to the address register circuit in response to the operation control mode.

12. The apparatus of claim 11, wherein the path circuit comprises:

a switch circuit for switching address transfer paths between the J temporary registers and the J address registers, in accordance with address switching information of the operation control mode.

14. The apparatus of claim 12, wherein the device further comprises:

a clock generating circuit for generating separately first and second clock signals to the command receiving circuit and the temporary holding circuit, respectively,

wherein,

the command receiving circuit registers and shifts the command in response to the first clock signal; and

the temporary holding circuit registers and shifts the stored bit streams in response to the second clock.

15. An apparatus for capturing data contained in a serial input (SI) in a plurality of devices in a serial interconnection configuration, each of the devices having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the apparatus being adopted in at least one of the devices, the apparatus comprising:

a serial input circuit (SI) for receiving the SI of command, address and data according to at least one pre-defined sequence and grouped as bytes in input bit streams representing the command, the address and the data;

a command receiving circuit for storing bit streams of the command;

a command interpreting circuit for decoding the command stored in the command receiving circuit;

a temporary holding circuit for storing input bit streams of the address temporarily, while the command is being decoded in the command interpreting circuit, wherein the temporary holding circuit comprises J temporary registers that are serially connected, so that one register forwards its stored bit stream to the next register

an address register circuit for storing the input bit streams temporarily stored in the temporary holding circuit to access the memory, wherein the address register circuit comprises J address registers for storing the input bit streams transferred from the J temporary registers, J being an integer greater than one; and

an address switching circuit for selectively connecting the held input bit streams to the address register circuit, in response to the command decoded by the interpreting circuit.

16. A method for capturing serial data in a plurality of devices in a serial interconnection configuration, each of the devices having a serial input connection for receiving serial input data and a serial output connection for providing serial output data, the method comprising:

receiving serial data input including a command, an address and data according to at least one pre-defined sequence and grouped as bytes in input bit data streams representing the command, the address and the data;

continuously storing an input bit data stream of the command in a command register;

decoding the command stored in the command register;

continuously storing the input bit data streams of the address temporarily in temporary registers, while the command is being decoded, wherein the temporary registers comprises J temporary registers that are serially connected, so that one register forwards its stored bit stream to the next register;

storing the input bit data streams in address registers to access the memory, wherein the address registers comprise J address registers for storing the address transferred from the J temporary registers, J being an integer greater than one; and

selectively connecting the temporary registers to the address registers, in response to the decoded command.