Isolation switching for backup memory

• US 8,904,099 B2
• Filed: 02/05/2014
• Issued: 12/02/2014
• Est. Priority Date: 06/01/2007
• Status: Active Grant

• Current Assignee: Netlist, Inc.
• Original Assignee: Netlist, Inc.
• Inventors: Chen, Chi-She, Solomon, Jeffrey C., Milton, Scott H., Bhakta, Jayesh
• Primary Examiner(s): Rojas, Midys
• Application Number:
  US14/173,219
• Publication Number:
  US 20140156919A1
• Time in Patent Office: 300 Days
• Field of Search: 711/100, 711/104, 711/111, 711/154, 711/160, 711/161, 711/162, 711/170, 711/171, 711/172
• US Class Current: 711/104
• CPC Class Codes: G06F 11/1072 in multilevel memories
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/2015 Redundant power supplies power supply failure G06F1/30
• CPC Class Codes: G06F 12/00 Accessing, addressing or allocating within memory systems or architectures digital input from, or digital output to record carriers, e.g. to disk storage units, G06F3/06
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/065 Replication mechanisms
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 5/141 Battery and back-up supplies
• CPC Class Codes: G11C 5/143 Detection of memory cassette insertion or removal; Continuity checks of supply or ground lines; Detection of supply variations, interruptions or levels G11C5/148 takes precedence; Switching between alternative supplies G11C5/141 takes precedence
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories

Abstract

Certain embodiments described herein include a memory system having a volatile memory subsystem, a non-volatile memory subsystem, a controller coupled to the non-volatile memory subsystem, and a circuit coupled to the volatile memory subsystem, to the controller, and to a host system. In a first mode of operation, the circuit is operable to selectively isolate the controller from the volatile memory subsystem, and to selectively couple the volatile memory subsystem to the host system to allow data to be communicated between the volatile memory subsystem and the host system. In a second mode of operation, the circuit is operable to selectively couple the controller to the volatile memory subsystem to allow data to be communicated between the volatile memory subsystem and the nonvolatile memory subsystem using the controller, and the circuit is operable to selectively isolate the volatile memory subsystem from the host system.

Claims

1. A memory module comprising:

a volatile memory subsystem having a first storage capacity;

a nonvolatile memory subsystem having a second storage capacity, the second storage capacity being at least 400 percent more than the first storage capacity, wherein the memory module is configured to provide non-volatile storage via the non-volatile memory subsystem;

a standard DIMM interface configured to electrically couple the memory module to a host system, the standard DIMM interface including an edge connector which fits into a memory socket of the host system, the edge connector including a plurality of edge connections to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and the host system, the first plurality of DDR SDRAM signals including at least address/control and data signals, wherein data is communicated between the volatile memory subsystem and the host system using the first signals path; and

a controller in communication with the volatile memory subsystem via a second signals path for transmitting a second plurality of DDR SDRAM signals between the controller and the volatile memory subsystem, the second plurality of DDR SDRAM signals including at least address/control and data signals, the controller being coupled to the nonvolatile memory subsystem via a third signals path for transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem, wherein the controller includes;

a logic element operable to generate address and control signals for the nonvolatile memory subsystem, wherein the logic element performs address-to-address translation between the volatile memory subsystem and the nonvolatile memory subsystem, and

a microcontroller operable to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem,

wherein the controller is configured (i) to communicate data with the volatile memory subsystem using the second plurality of DDR SDRAM signals via the second signals path, and (ii) to communicate data with the nonvolatile memory subsystem using the at least data, address and control signals via the third signals path.

2. The memory module of claim 1, wherein the controller is operable to perform signal level translation between the at least data, address and control signals transmitted to the nonvolatile memory subsystem via the third signals path and the second plurality of DDR SDRAM signals transmitted to the volatile memory subsystem via the second signals path.

3. The memory module of claim 1, wherein, in response to a request by the host system, the controller transfers data from the volatile memory subsystem into the nonvolatile memory subsystem.

4. The memory module of claim 1, wherein the controller performs memory management for the nonvolatile memory subsystem, the memory management including bad-block management and error management for memory elements of the nonvolatile memory subsystem.

5. The memory module of claim 4, wherein the controller performs error detection/correction on each data word transferred from the volatile memory subsystem into the nonvolatile memory subsystem.

6. The memory module of claim 1, wherein the standard DIMM interface includes a standard DIMM interface of any one of a registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), an unbuffered DIMM (UDIMM), a mini-DIMM, a mini-RDIMM, a very low profile mini-DIMM, and a micro-DIMM.

7. The memory module of claim 1, wherein the nonvolatile memory subsystem comprises one or more flash memory elements, wherein the one or more flash memory elements include one or more of multi-level cell (MLC), NOR, ONE-NAND, and NAND flash memory elements.

8. The memory module of claim 1, wherein the controller includes a voltage monitor circuit to monitor a first voltage received from the host system via the standard DIMM interface, the voltage monitor circuit operable to transmit a first signal to other portions of the controller upon detecting a power threshold condition, and the controller further operable to respond to the first signal by accessing data on the volatile memory system and by executing a write cycle on the nonvolatile memory subsystem.

9. The memory module of claim 8, wherein executing a write cycle on the nonvolatile memory system includes transferring data from the volatile memory subsystem to the nonvolatile memory subsystem via the controller.

10. The memory module of claim 8, further comprising:

at least one capacitor configured to store a second voltage, wherein in response to the first signal, the second voltage is used to provide power to the memory module.

11. The memory module of claim 1, wherein the circuit includes dynamic on-die termination.

12. The memory module of claim 1, wherein the controller is operable to transfer data from the volatile memory subsystem into the nonvolatile memory subsystem in response to any one of a power interruption, a power failure, a power reduction, a hang-up of the host system, a reboot condition, detecting that a voltage received from the host system is below a certain threshold voltage, detecting that a voltage received from the host system is above a certain threshold voltage, or detecting that a voltage received from the host system is below a first threshold voltage and above a second threshold voltage.

13. The memory module of claim 1, wherein the volatile memory subsystem comprises two or more DDR SDRAM memory elements.

14. The memory module of claim 1, wherein the volatile memory subsystem comprises a plurality of volatile memory elements.

15. The memory module of claim 1, further comprising:

a circuit coupled to the volatile memory subsystem via a fourth signals path, coupled to the controller via the second signals path, and coupled to the standard DIMM interface via the first signals path, wherein in response to a signal from the controller the circuit allows data to be communicated (i) between the volatile memory subsystem and the host via the first signals path, and (ii) between the volatile memory subsystem and the nonvolatile memory subsystem via the second signals path.

16. A method for operating a memory module having a volatile memory subsystem with a first storage capacity and a nonvolatile memory subsystem with a second storage capacity that is at least 400 percent more than the first storage capacity, the memory module operable to provide non-volatile storage via the non-volatile memory subsystem and having a standard DIMM interface that is configured to electrically couple the memory module to a host system, the standard DIMM interface including an edge connector which fits into a memory socket of the host system and which has a plurality of edge connections to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and the host system, the first plurality of DDR SDRAM signals including at least address/control and data signals, wherein data is communicated between the volatile memory subsystem and the host system using the first signals path, the memory module further having a controller with a logic element and a microcontroller, the method comprising:

coupling the controller to the volatile memory subsystem via a second signals path;

transmitting a second plurality of DDR SDRAM signals between the controller and the volatile memory subsystem via the second signals path, wherien the second plurality of DDR SDRAM signals includes at least address/control and data signals;

coupling the controller to the nonvolatile memory subsystem via a third signals path;

transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem via the third signals path;

using the logic element to generate address and control signals for the nonvolatile memory subsystem, wherein the logic element performs address to address translation between the volatile memory subsystem and the nonvolatile memory subsystem;

using the microcontroller to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem; and

using the controller (i) to communicate data with the volatile memory subsystem using the second plurality of DDR SDRAM signals via the second signals path, and (ii) to communicate data with the nonvolatile memory subsystem using the at least data, address and control signals via the third signals path.

17. The method of claim 16, further comprising operating the controller to perform signal level translation between the at least data, address and control signals and the second plurality of DDR SDRAM signals.

18. The method of claim 16, further comprising, in response to a request by the host system, operating the controller to transfer data from the volatile memory subsystem into the nonvolatile memory subsystem.

19. The method of claim 16, further comprising using the controller to perform memory management for the nonvolatile memory subsystem, the memory management including bad-block management and error management for memory elements of the nonvolatile memory subsystem.

20. The method of claim 19, further comprising using the controller to perform error detection/correction on each data word transferred from the volatile memory subsystem into the nonvolatile memory subsystem.

21. The method of claim 16, wherein the standard DIMM interface includes a standard DIMM interface of any one of a registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), an unbuffered DIMM (UDIMM), a mini-DIMM, a mini-RDIMM, a very low profile mini-DIMM, and a micro-DIMM.

22. The method of claim 16, wherein the nonvolatile memory subsystem comprises one or more flash memory elements, wherein the one or more flash memory elements include one or more of multi-level cell (MLC), NOR, ONE-NAND, and NAND flash memory elements.

23. The method of claim 16, wherein the controller includes a voltage monitor circuit to monitor a first voltage received from the host system via the standard DIMM interface, the voltage monitor circuit operable to transmit a first signal to other portions of the controller upon detecting a power threshold condition, and the controller further operable to respond to the first signal by accessing data on the volatile memory system and by executing a write cycle on the nonvolatile memory subsystem.

24. The method of claim 23, wherein executing a write cycle on the nonvolatile memory system includes transferring data from the volatile memory subsystem to the nonvolatile memory subsystem via the controller.

25. The method of claim 23, wherein the memory module includes at least one capacitor configured to store a second voltage, wherein in response to the first signal, the second voltage is used to provide power to the memory module.

26. The method of claim 16, further comprising operating the controller to transfer data from the volatile memory subsystem into the nonvolatile memory subsystem in response to any one of a power interruption, a power failure, a power reduction, a hang-up of the host system, a reboot condition, detecting that a voltage received from the host system is below a certain threshold voltage, detecting that a voltage received from the host system is above a certain threshold voltage, or detecting that a voltage received from the host system is below a first threshold voltage and above a second threshold voltage.

27. The method of claim 16, wherein the volatile memory subsystem comprises two or more DDR SDRAM memory elements.

28. The method of claim 16, wherein the volatile memory subsystem comprises a plurality of volatile memory elements.

29. The method of claim 16, wherein the coupling of the controller to the volatile memory subsystem via a second signals path further comprising:

coupling the volatile memory subsystem to a circuit via a fourth signals path;

coupling the circuit to the controller via the second signals path; and

coupling the circuit to the standard DIMM interface via the first signals path, wherein, in response to a signal from the controller, the circuit allows data to be communicated (i) between the volatile memory subsystem and the host via the first signals path, and (ii) between the volatile memory subsystem and the nonvolatile memory subsystem via the second signals path.

30. The method of claim 29, wherein the circuit includes dynamic on-die termination.

31. A nontransitory computer readable storage medium storing one or more programs configured to be executed by one or more computing devices, said programs, when executing on the one or more computing devices, causing performance of a method for operating a memory module having a volatile memory subsystem with a first storage capacity and a nonvolatile memory subsystem with a second storage capacity that is at least 400 percent more than the first storage capacity, the memory module operable to provide non-volatile storage via the non-volatile memory subsystem and having a standard DIMM interface that is configured to electrically couple the memory module to a host system, the standard DIMM interface including an edge connector which fits into a memory socket of the host system and which has a plurality of edge connections to provide a first signals path for transmitting a first plurality of dual data rate synchronous DRAM (DDR SDRAM) signals between the memory module and the host system, the first plurality of DDR SDRAM signals including at least address/control and data signals, wherein data is communicated between the volatile memory subsystem and the host system using the first signals path, the memory module further having a controller with a logic element and a microcontroller, the method comprising:

coupling the controller to the volatile memory subsystem via a second signals path;

transmitting a second plurality of DDR SDRAM signals between the controller and the volatile memory subsystem via the second signals path, wherien the second plurality of DDR SDRAM signals includes at least address/control and data signals;

coupling the controller to the nonvolatile memory subsystem via a third signals path;

transmitting at least data, address and control signals between the controller and the nonvolatile memory subsystem via the third signals path;

using the logic element to generate address and control signals for the nonvolatile memory subsystem, wherein the logic element performs address to address translation between the volatile memory subsystem and the nonvolatile memory subsystem;

using the microcontroller to control data transfer between the volatile memory subsystem and the nonvolatile memory subsystem; and

using the controller (i) to communicate data with the volatile memory subsystem using the second plurality of DDR SDRAM signals via the second signals path, and (ii) to communicate data with the nonvolatile memory subsystem using the at least data, address and control signals via the third signals path.

32. The nontransitory computer readable storage medium of claim 31, wherein the method further comprises operating the controller to perform signal level translation between the at least data, address and control signals and the second plurality of DDR SDRAM signals.

33. The nontransitory computer readable storage medium of claim 31, wherein the method further comprises, in response to a request by the host system, operating the controller to transfer data from the volatile memory subsystem into the nonvolatile memory subsystem.

34. The nontransitory computer readable storage medium of claim 31, wherein the method further comprises using the controller to perform memory management for the nonvolatile memory subsystem, the memory management including bad-block management and error management for memory elements of the nonvolatile memory subsystem.

35. The nontransitory computer readable storage medium of claim 34, wherein the method further comprises using the controller to perform error detection/correction on each data word transferred from the volatile memory subsystem into the nonvolatile memory subsystem.

36. The nontransitory computer readable storage medium of claim 31, wherein the standard DIMM interface includes a standard DIMM interface of any one of a registered DIMM (RDIMM), a small-outline DIMM (SO-DIMM), an unbuffered DIMM (UDIMM), a mini-DIMM, a mini-RDIMM, a very low profile mini-DIMM, and a micro-DIMM.

37. The nontransitory computer readable storage medium of claim 31, wherein the nonvolatile memory subsystem comprises one or more flash memory elements, wherein the one or more flash memory elements include one or more of multi-level cell (MLC), NOR, ONE-NAND, and NAND flash memory elements.

38. The nontransitory computer readable storage medium of claim 31, wherein the controller includes a voltage monitor circuit to monitor a first voltage received from the host system via the standard DIMM interface, the voltage monitor circuit operable to transmit a first signal to other portions of the controller upon detecting a power threshold condition, and the controller further operable to respond to the first signal by accessing data on the volatile memory system and by executing a write cycle on the nonvolatile memory subsystem.

39. The nontransitory computer readable storage medium of claim 38, wherein executing a write cycle on the nonvolatile memory system includes transferring data from the volatile memory subsystem to the nonvolatile memory subsystem via the controller.

40. The nontransitory computer readable storage medium of claim 38, wherein the memory module includes at least one capacitor configured to store a second voltage, wherein in response to the first signal, the second voltage is used to provide power to the memory module.

41. The nontransitory computer readable storage medium of claim 31, wherein the method further comprises operating the controller to transfer data from the volatile memory subsystem into the nonvolatile memory subsystem in response to any one of a power interruption, a power failure, a power reduction, a hang-up of the host system, a reboot condition, detecting that a voltage received from the host system is below a certain threshold voltage, detecting that a voltage received from the host system is above a certain threshold voltage, or detecting that a voltage received from the host system is below a first threshold voltage and above a second threshold voltage.

42. The nontransitory computer readable storage medium of claim 31, wherein the volatile memory subsystem comprises two or more DDR SDRAM memory elements.

43. The nontransitory computer readable storage medium of claim 31, wherein the volatile memory subsystem comprises a plurality of volatile memory elements.

44. The nontransitory computer readable medium of claim 31, wherein the coupling of the controller to the volatile memory subsystem via a second signals path further comprises:

coupling the volatile memory subsystem to a circuit via a fourth signals path;

coupling the circuit to the controller via the second signals path; and

coupling the circuit to the standard DIMM interface via the first signals path, and wherein, in response to a signal from the controller, the circuit allows data to be communicated (i) between the volatile memory subsystem and the host via the first signals path, and (ii) between the volatile memory subsystem and the nonvolatile memory subsystem via the second signals path.

45. The nontransitory computer readable storage medium of claim 31, wherein the circuit includes dynamic on-die termination.