Cache with multiple access pipelines

• US 8,904,115 B2
• Filed: 08/18/2011
• Issued: 12/02/2014
• Est. Priority Date: 09/28/2010
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chachad, Abhijeet Ashok, Damodaran, Raguram, Tran, Jonathan (Son) Hung, Anderson, Timothy David, Agarwala, Sanjive
• Primary Examiner(s): Blair, April Y
• Assistant Examiner(s): Thammavong, Prasith
• Application Number:
  US13/212,895
• Publication Number:
  US 20120079204A1
• Time in Patent Office: 1,202 Days
• Field of Search: 711/130
• US Class Current: 711/130
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: G06F 11/1064 in cache or content addressable memories
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/1081 for peripheral access to main memory, e.g. direct memory access [DMA]
• CPC Class Codes: G06F 12/12 Replacement control
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 13/1652 in a multiprocessor architecture interprocessor communication using common memory G06F15/167
• CPC Class Codes: G06F 13/1657 Access to multiple memories
• CPC Class Codes: G06F 13/1663 Access to shared memory
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G06F 2212/221 Static RAM
• CPC Class Codes: G06F 2212/2532 comprising a plurality of modules
• CPC Class Codes: G06F 2212/283 Plural cache memories
• CPC Class Codes: G06F 2212/608 Details relating to cache mapping
• CPC Class Codes: G06F 7/483 Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers G06F7/4806, G06F7/4824, G06F7/49, G06F7/491, G06F7/544 take precedence
• CPC Class Codes: G06F 9/3012 : Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: H03K 19/0016 : by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 21/00 : Details of pulse counters or frequency dividers
• CPC Class Codes: H03M 13/2903 : Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
• CPC Class Codes: H03M 13/353 : Adaptation to the channel
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 : in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

Parallel pipelines are used to access a shared memory. The shared memory is accessed via a first pipeline by a processor to access cached data from the shared memory. The shared memory is accessed via a second pipeline by a memory access unit to access the shared memory. A first set of tags is maintained for use by the first pipeline to control access to the cache memory, while a second set of tags is maintained for use by the second pipeline to access the shared memory. Arbitrating for access to the cache memory for a transaction request in the first pipeline and for a transaction request in the second pipeline is performed after each pipeline has checked its respective set of tags.

Claims

1. A digital system comprising:

a shared resource including a cache subsystem having a shared memory, a first set of access tags and a duplicate second set of access tags;

a first access pipeline coupled to the shared resource, the first access pipeline being configured to receive a first transaction request from a first requester for access to the shared resource, wherein the first access pipeline includes a stall stage that is coupled to the first set of access tags and configured to stall when the first set of access tags indicate a miss in response to the first transaction request;

a second access pipeline coupled to the shared resource, the second access pipeline being configured to receive a second transaction request from a second requester for access to the shared resource, wherein the second access pipeline includes a check stage that is coupled to the second set of access tags, configured to check the second set of access tags and cancel the second transmission request if access is denied; and

arbitration logic configured to control access to the shared resource coupled to the first access pipeline and to the second access pipeline, wherein the arbitration logic is coupled to the first access pipeline after the stall stage and coupled to the second access pipeline after the check stage.

2. The system of claim 1, wherein:

the arbitration logic includes weighting logic configured to grant access to the shared resource in response to a weighting value stored in a program writable weighting register.