Processor architecture with switch matrices for transferring data along buses

• US 8,904,148 B2
• Filed: 07/05/2011
• Issued: 12/02/2014
• Est. Priority Date: 12/19/2000
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Claydon, Anthony Peter John, Claydon, Anne Patricia
• Primary Examiner(s): Caldwell, Andrew
• Assistant Examiner(s): GEIB, BENJAMIN P
• Application Number:
  US13/176,381
• Publication Number:
  US 20120191945A1
• Time in Patent Office: 1,246 Days
• Field of Search: 712/11, 712/18
• US Class Current: 712/11
• CPC Class Codes: G06F 15/8023 Two dimensional arrays, e.g. mesh, torus

Abstract

There is described a processor architecture, comprising: a plurality of first bus pairs, each first bus pair including a respective first bus running in a first direction (for example, left to right) and a respective second bus running in a second direction opposite to the first direction (for example right to left); a plurality of second bus pairs, each second bus pair including a respective third bus running in a third direction (for example downwards) and a respective fourth bus running in a fourth direction opposite to the third direction (for example upwards), the third and fourth buses intersecting the first and second buses; a plurality of switch matrices, each switch matrix located at an intersection of a first and a second pair of buses; a plurality of elements arranged in an array, each element being arranged to receive data from a respective first or second bus, and transfer data to a respective first or second bus. The elements in the array include processing elements, for operating on received data, and memory elements, for storing received data. The described architecture has the advantage that it requires relatively little memory, and the memory requirements can be met by local memory elements in the array.

Claims

1. A processor architecture comprising:

a plurality of array elements arranged in an array; and

at least one switch matrix configured to route data between the array elements;

wherein the processor architecture is configured such that the at least one switch matrix is switched to transfer the data in a series of predetermined cyclical patterns, which are repeated, to provide transfer cycles that occur at predetermined times such that the array elements are synchronized to the transfer cycles and to execute instructions as a result of receiving data.

2. The processor architecture of claim 1 further comprising at least one switch control array element configured to control the at least one switch matrix to provide the transfer cycles.

3. The processor architecture of claim 2, wherein the at least one switch control array element is configured to control the at least one switch matrix to route data based on data stored in a local memory of the switch control array element.

4. The processor architecture of claim 2, wherein the at least one switch control array element is configured to control the at least one switch matrix to route data from one or more source array elements to more than one destination array element.

5. The processor architecture of claim 1 further comprising a plurality of buses, wherein the array elements are configured to transfer data to and receive data from the plurality of buses.

6. The processor architecture of claim 5, wherein the at least one switch matrix is configured to route data input to the switch matrix on one bus to be output from the matrix on more than one bus.

7. The processor architecture of claim 5, wherein the at least one switch matrix is configured to route data from one or more input buses to be output from the matrix on one or more output buses.

8. The processor architecture of claim 5, wherein said plurality of buses comprise multi-bit buses and wherein the processor architecture is configured such that several array elements can source data onto the same bus in the same transfer cycle using different fields of the multi-bit bus.

9. The processor architecture of claim 8, wherein the multi-bit bus is a 64-bit bus and wherein one array element is configured to transfer data to only some of the bits of the 64-bit bus.

10. The processor architecture of claim 1, wherein data is passed from one array element to another without being written to memory.

11. The processor architecture of claim 1, wherein the array elements are configured to be data driven such that the array elements only execute instructions of their programs when data arrives.

12. The processor architecture of claim 1, wherein the plurality of array elements comprise at least one array element having hardware elements configured to perform signal processing functions.

13. The processor architecture of claim 12, wherein the hardware elements comprise one or both of an analog-digital convertor or a digital-analog converter.

14. The processor architecture of claim 1, wherein the plurality of array elements comprise at least one array element having a predefined hardware function.

15. The processor architecture of claim 1, wherein the plurality of array elements comprise processor elements, memory elements, switch array control elements and interface elements.

16. A processor architecture comprising:

a plurality of array elements arranged in an array;

at least one switch matrix configured to route data between the array elements; and

at least one switch control array element configured to control the at least one switch matrix based on received data that is to be processed by the array elements, wherein the processor architecture is configured such that the at least one switch matrix is switched in a cyclical pattern, which is automatically repeated during operation, to provide transfer cycles that repeatedly occur at predetermined times and wherein the array elements are synchronized to the transfer cycles.

17. A processor architecture comprising:

a plurality of array elements arranged in an array configured to process data; and

at

least one switch matrix configured to route the data between the array elements;

a first bus, configured to connect to and carry the data to at least one of the plurality of array elements;

at least one switch matrix control element configured to access the first bus to obtain the data, the data controls the switch matrix control element to thereby control switching of the at least one switch matrix, wherein the processor architecture is configured such that the at least one switch matrix is switched in a cyclical pattern, which is repeated, to provide transfer cycles that occur at predetermined times and wherein the array elements are synchronized to the transfer cycles.