Pulsed dielectric etch process for in-situ metal hard mask shape control to enable void-free metallization

• US 8,906,810 B2
• Filed: 05/07/2013
• Issued: 12/09/2014
• Est. Priority Date: 05/07/2013
• Status: Active Grant

• Current Assignee: Lam Research Corporation
• Original Assignee: Lam Research Corporation
• Inventors: Indrakanti, Ananth, Nagabhirava, Bhaskar, Jensen, Alan, Choi, Tom
• Primary Examiner(s): Vinh, Lan
• Assistant Examiner(s): Lu, Jiong-Ping
• Application Number:
  US13/888,901
• Publication Number:
  US 20140335697A1
• Time in Patent Office: 581 Days
• US Class Current: 438/715
• CPC Class Codes: H01L 21/02063 the processing being the formation of vias or contact holes
• CPC Class Codes: H01L 21/31116 by dry-etching
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32136 using plasmas
• CPC Class Codes: H01L 21/67109 mainly by convection
• CPC Class Codes: H01L 21/67248 Temperature monitoring
• CPC Class Codes: H01L 21/6831 using electrostatic chucks
• CPC Class Codes: H01L 21/76811 involving multiple stacked pre-patterned masks
• CPC Class Codes: H01L 21/76813 involving a partial via etch

Abstract

An all-in-one trench-over-via etch wherein etching of a low-k material beneath a metal hard mask of titanium nitride containing material is carried out in alternating steps of (a) etching the low-k material while maintaining chuck temperature at about 45 to 80° C. and (b) metal hard mask rounding and Ti-based residues removal while maintaining chuck temperature at about 90 to 130° C.

Claims

1. A method of etching self-aligned vias and trenches in a multi-layer film stack supported by a temperature controlled electrostatic chuck in a plasma processing apparatus wherein the temperature controlled electrostatic chuck adjusts the temperature of the multi-layer film stack during etching of the self-aligned vias and trenches, the method comprising alternating steps of

(a) etching low-k material beneath a metal hard mask (MHM) of titanium nitride containing material while maintaining the chuck at about 45 to 80°

C. and

(b) MHM rounding and Ti-based residues removal while maintaining the chuck at about 90 to 130°

C. and

repeating (a) and (b) at least once;

wherein the low-k material and the metal hard mask in the repeating step (a) are the same as the low-k material and the metal hard mask in the original step (a).

2. The method of claim 1, wherein the metal hard mask is preferably formed from a material selected from the group consisting of TiN, TiSiN, TiTaN, TiON and combinations thereof.

3. The method of claim 1, wherein the metal hard mask layer is TiN.

4. The method of claim 1, wherein steps (a) and (b) are preferably carried out in a capacitively coupled plasma chamber, during step (a) 27 and 60 MHz RF power is supplied at about 300 to 500 watts and the chamber at a vacuum pressure of about 40 to 80 mTorr while supplying process gas comprising C_xF_yH_z(x≧

1, y≧

1, z≧

0), an oxygen containing gas and a nitrogen containing gas for 10 to 30 seconds and during step (b) 60 MHz RF power is supplied at about 100 to 300 watts and the chamber is at a vacuum pressure of about 20 to 40 mTorr while supplying an oxygen free process gas comprising C_xF_y (x≧

1, y≧

1) and a nitrogen containing gas for 10 to 30 seconds.

5. The method of claim 4, wherein during step (a) the process gas is C₄F₈, CO, N₂ and Ar and during step (b) the oxygen-free process gas is CF₄ and N₂ or CF₄ and NH₃.

6. The method of claim 1, wherein the plasma etch reactor comprises a dual-frequency medium-density capacitively coupled plasma reactor including an upper showerhead electrode and a bottom electrode, and during step (a) a 2 MHz RF bias is supplied to the bottom electrode at about 100 to 200 watts.

7. The method of claim 1, wherein steps (a) and (b) are carried out for a total time of up to 60 seconds with a time ratio of step (a)/step (b) of 1:

3 to 3;

1.

8. The method of claim 1, wherein upon completion of steps (a) and (b) corners of the metal hard mask are rounded and undercutting of the low-k material beneath the metal hard mask is avoided.

9. The method of claim 1, wherein etch selectivity of the TiN material is at least 5:

1 (etch rate of low-k/etch rate of TiN) during step (a) and the etch selectivity is about 0.5;

1 to 2;

1 (etch rate of low-k/etch rate of TiN) during step (b).

10. The method of claim 1, wherein steps (a) and (b) are repeated two to four times.

11. The method of claim 1, further comprising:

etching via openings into a planarization layer beneath a previously patterned photo resist mask while maintaining the multi-layer film stack at a temperature of about 30 to 50°

C., the planarization layer overlying and filling trench openings in a metal hard mask previously patterned to form trenches, the via openings in the planarization layer being larger than the trench openings, the etching being carried out until planarization material in the trench openings is removed and elliptical via openings are formed in areas of the trench openings where the planarization material is removed;

etching elliptical via openings into a hard mask layer beneath the metal hard mask while maintaining the multi-layer film stack at a temperature of about 0 to 20°

C.;

etching elliptical via openings into a dielectric layer beneath the hard mask layer by transferring the pattern of elliptical via openings in the hard mask layer into the dielectric layer and continuing the etching until the elliptical via openings reach an etch stop layer beneath the dielectric layer while the multi-layer stack is maintained at a temperature below about 60°

C.;

stripping the planarization layer to expose the pattern of trench openings in the metal hard mask;

etching trenches into the dielectric layer by transferring the pattern of trench openings in the hard mask layer into the dielectric layer, while etching the elliptical via openings through the etch stop layer.

12. The method of claim 11, further comprising etching the elliptical via openings into a dielectric barrier layer beneath the etch stop layer while the multi-layer stack is maintained at a temperature of above about 40°

C.

13. The method of claim 11, wherein the photo resist mask is above a silicon containing anti-reflective coating (SiARC), and the planarization layer is an organic planarization layer (OPL).

14. The method of claim 13, wherein the patterned hard mask layer includes a lower hard mask (HM1) layer, a metal hard mask (MHM) layer over the HM1 layer, and an upper hard mask (HM2) layer over the MHM layer, the MHM layer and the HM2 layer including the patterned trench openings, the method including transferring the elliptical via openings into the HM1 layer.

15. The method of claim 11, wherein the elliptical via openings have vertical sidewalls.

16. The method of claim 11, wherein a silicon containing antireflection layer (SiARC) is beneath the photo resist mask and the hard mask layer includes a TiN layer between upper and lower silicon containing hard mask layers, the method including transferring the via openings into the SiARC prior to transferring the via openings into the planarization layer and transferring the elliptical via openings into the lower silicon containing hard mask layer prior to transferring the elliptical via openings into the dielectric layer.

17. The method of claim 11, wherein the multilayer stack includes an etch stop layer beneath the dielectric layer and a barrier layer below the etch stop layer, the method including transferring the elliptical via openings into the etch stop layer before stripping the planarization layer, extending the elliptical via openings through the etch stop layer during the step of transferring the trench openings into the dielectric layer, and subsequently transferring the elliptical via openings into the barrier layer.